@@ -297,8 +297,13 @@ namespace CallingConv {
/// directly or indirectly via a call-like instruction.
constexpr bool isCallableCC(CallingConv::ID CC) {
switch (CC) {
+ // Called with special intrinsics:
+ // llvm.amdgcn.cs.chain
case CallingConv::AMDGPU_CS_Chain:
case
https://github.com/rovka ready_for_review
https://github.com/llvm/llvm-project/pull/145860
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https://github.com/rovka ready_for_review
https://github.com/llvm/llvm-project/pull/145859
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rovka wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145859?utm_source=stack-comment-downstack-mergeability-warning";
>
rovka wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145860?utm_source=stack-comment-downstack-mergeability-warning";
>
https://github.com/rovka approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/142603
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https://github.com/rovka closed https://github.com/llvm/llvm-project/pull/136847
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https://github.com/llvm/llvm-project/pull/136847
None
>From c2050bc0bf85542524e1ed3c7bf2d1fb286145df Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Wed, 23 Apr 2025 13:14:37 +0200
Subject: [PATCH] Fix formatting
---
llvm/lib/CodeGen/PrologEpilogInserter.cpp
rovka wrote:
Reopening this (not sure if I can change the target branch)
https://github.com/llvm/llvm-project/pull/131329
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https://github.com/rovka closed https://github.com/llvm/llvm-project/pull/131329
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rovka wrote:
Oh, oops, I think this got closed automatically when I merged my branch into
main. Can you please reopen and update the branch to main? Thanks!
https://github.com/llvm/llvm-project/pull/131329
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@@ -1452,6 +1452,16 @@ bool GCNSchedStage::shouldRevertScheduling(unsigned
WavesAfter) {
if (WavesAfter < DAG.MinOccupancy)
return true;
+ // For dynamic VGPR mode, we don't want to waste any VGPR blocks.
+ if (ST.isDynamicVGPREnabled()) {
rovka wrote
@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB,
MachineInstr &MI,
MDT->applyUpdates(DTUpdates);
}
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+ if (Op.isReg
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/8] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
@@ -1200,34 +1225,78 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
@@ -736,6 +742,26 @@ multiclass si_cs_chain_tc_patterns<
defm : si_cs_chain_tc_patterns;
defm : si_cs_chain_tc_patterns;
+// Match dynamic VGPR case. This is always indirect since we choose the callee
+// dynamically based on the result of the VGPR reallocation, so make sure t
@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB,
MachineInstr &MI,
MDT->applyUpdates(DTUpdates);
}
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+ if (Op.isReg
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/4] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/5] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/3] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/2] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
rovka wrote:
Ping?
https://github.com/llvm/llvm-project/pull/130094
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rovka wrote:
> Is there any test for the revert scheduling portion of the change?
Sadly, no. It's a bit difficult to add.
https://github.com/llvm/llvm-project/pull/130047
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@@ -511,6 +511,14 @@ SIRegisterInfo::getLargestLegalSuperClass(const
TargetRegisterClass *RC,
Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/7] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
@@ -0,0 +1,263 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+dynamic-vgpr < %s
| FileCheck -check-prefix=CHECK %s
+
+; Make sure we use a stack pointer and allo
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/6] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
@@ -1239,6 +1239,12 @@ def FeatureXF32Insts : SubtargetFeature<"xf32-insts",
"v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32"
>;
+def FeatureDynamicVGPR : SubtargetFeature <"dynamic-vgpr",
rovka wrote:
That's right, this is enabled from above the bac
rovka wrote:
> It seems to me this should be a separate attribute, it's not really part of
> the target
I don't really disagree with that. I think I made it a feature because it's
kind of a hardware mode (i.e. it takes over a CU, and waves that use dynamic
VGPRs can't be mixed with waves that
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130037
>From c29d8202c06488a9466aea49dda4cf2b4663236e Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Mon, 23 Oct 2023 11:46:19 +0200
Subject: [PATCH 1/2] [AMDGPU] Deallocate VGPRs before exiting in dynamic VGPR
mode
https://github.com/rovka edited https://github.com/llvm/llvm-project/pull/130047
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https://github.com/rovka created
https://github.com/llvm/llvm-project/pull/130047
In dynamic VGPR mode, we can allocate up to 8 blocks of either 16 or 32 VGPRs
(based on a chip-wide setting which we can model with a Subtarget feature).
Update some of the subtarget helpers to reflect this.
In
https://github.com/rovka created
https://github.com/llvm/llvm-project/pull/130030
This represents a hardware mode supported only for wave32 compute shaders. When
enabled, we set the `.dynamic_vgpr_en` field of `.compute_registers` to true in
the PAL metadata.
>From b2a7bdc3954d2bf72e99d730ce0
@@ -2773,6 +2773,9 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode
*N) {
case Intrinsic::amdgcn_wwm:
case Intrinsic::amdgcn_strict_wwm:
Opcode = AMDGPU::STRICT_WWM;
+CurDAG->getMachineFunction()
+.getInfo()
+->setInitWholeWave();
---
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
@@ -26,6 +28,26 @@ std::pair
getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
GISelKnownBits *KnownBits = nullptr,
bool CheckNUW = false);
+
+// Currently finds S32/S64 lane masks that can be declared as diver
@@ -63,4 +70,189 @@ char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
-bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }
+bool shouldRBSelect(MachineInstr &MI) {
+
Author: Diana Picus
Date: 2022-02-10T09:31:38+01:00
New Revision: e77317a786b0c6d4489de0e6679128baf363498e
URL:
https://github.com/llvm/llvm-project/commit/e77317a786b0c6d4489de0e6679128baf363498e
DIFF:
https://github.com/llvm/llvm-project/commit/e77317a786b0c6d4489de0e6679128baf363498e.diff
L
Author: Diana Picus
Date: 2021-07-29T10:28:39+02:00
New Revision: 01dd37be9baea020b638d04c5523e153b1a102f9
URL:
https://github.com/llvm/llvm-project/commit/01dd37be9baea020b638d04c5523e153b1a102f9
DIFF:
https://github.com/llvm/llvm-project/commit/01dd37be9baea020b638d04c5523e153b1a102f9.diff
L
Author: rovka
Date: Fri Jan 20 05:38:10 2017
New Revision: 292603
URL: http://llvm.org/viewvc/llvm-project?rev=292603&view=rev
Log:
Fix wrapping in ReleaseNotes.rst. NFC.
Modified:
llvm/branches/release_40/docs/ReleaseNotes.rst
Modified: llvm/branches/release_40/docs/ReleaseNotes.rst
URL:
h
Author: rovka
Date: Fri Jan 20 05:34:32 2017
New Revision: 292602
URL: http://llvm.org/viewvc/llvm-project?rev=292602&view=rev
Log:
Add some release notes for ARM and AArch64
Modified:
llvm/branches/release_40/docs/ReleaseNotes.rst
Modified: llvm/branches/release_40/docs/ReleaseNotes.rst
URL
Author: rovka
Date: Wed Aug 3 07:00:27 2016
New Revision: 277590
URL: http://llvm.org/viewvc/llvm-project?rev=277590&view=rev
Log:
Add a few things to the AArch64 release notes
Modified:
llvm/branches/release_39/docs/ReleaseNotes.rst
Modified: llvm/branches/release_39/docs/ReleaseNotes.rst
Author: rovka
Date: Tue Aug 2 09:34:15 2016
New Revision: 277462
URL: http://llvm.org/viewvc/llvm-project?rev=277462&view=rev
Log:
Merging r277457
[clang-cl] Fix PCH tests to use x86_64 as target
These tests require x86-registered-target, but they don't force the target as
x86 on the command li
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