https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/115185
>From 9cf30ea74f2f0d4ddc042224c65811ce682f0275 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 21 Oct 2024 17:56:40 +0300
Subject: [PATCH 1/2] [AArch64][PAC] Eliminate excessive MOVs when comput
atrosinenko wrote:
@kovdan01 Thank you for the review, I have just pushed the commit that should
resolve the comments.
Additionally, I discovered that I misunderstood BRA pseudo to be kind of tail
call instruction - it is actually used for computed goto. While my original
changes are still ha
@@ -163,8 +163,15 @@ class AArch64AsmPrinter : public AsmPrinter {
// Emit the sequence for AUT or AUTPAC.
void emitPtrauthAuthResign(const MachineInstr *MI);
- // Emit the sequence to compute a discriminator into x17, or reuse AddrDisc.
- unsigned emitPtrauthDiscriminat
@@ -188,6 +188,33 @@ define void @test_tailcall_omit_mov_x16_x16(ptr %objptr)
#0 {
ret void
}
+define i32 @test_call_omit_extra_moves(ptr %objptr) #0 {
atrosinenko wrote:
Initially, I tried to implement a separate test case for tail calls, but then
realiz
@@ -163,8 +163,15 @@ class AArch64AsmPrinter : public AsmPrinter {
// Emit the sequence for AUT or AUTPAC.
void emitPtrauthAuthResign(const MachineInstr *MI);
- // Emit the sequence to compute a discriminator into x17, or reuse AddrDisc.
- unsigned emitPtrauthDiscriminat
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/115185
>From c4fa68c7ad66911e006c175ec9acf9e3cca9c1d9 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 21 Oct 2024 17:56:40 +0300
Subject: [PATCH 1/2] [AArch64][PAC] Eliminate excessive MOVs when comput
https://github.com/atrosinenko ready_for_review
https://github.com/llvm/llvm-project/pull/115185
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atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115185?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/115185
As function calls do not generally preserve X16 and X17, it is beneficial
to allow AddrDisc operand of B(L)RA instruction to reside in these
registers and make use of this condition when computing the discrim
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110705
>From aec7d908c567a857d63a731eab044bbdd2925558 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 23 Sep 2024 19:51:55 +0300
Subject: [PATCH 1/3] [AArch64][PAC] Move emission of LR checks in tail c
@@ -107,6 +107,19 @@ unsigned AArch64InstrInfo::getInstSizeInBytes(const
MachineInstr &MI) const {
unsigned NumBytes = 0;
const MCInstrDesc &Desc = MI.getDesc();
+ if (!MI.isBundle() && isTailCallReturnInst(MI)) {
+NumBytes = Desc.getSize() ? Desc.getSize() : 4;
+
+
atrosinenko wrote:
@kovdan01 Considering incorrectly choosing the scratch register, I doubt I can
implement a test that is reliable: with my particular fix, it would require
crafting an example that is *likely* to be emitted as an `AUTH_TCRETURN*` with
AddrDisc operand being x16. I cannot simp
atrosinenko wrote:
Considering the reproducer, the code became a bit longer but correct:
```
_ZN7myshape4moveEv: // @_ZN7myshape4moveEv
.cfi_startproc
// %bb.0: // %entry
.cfi_b_key_frame
pacibsp
stp x30, x19,
atrosinenko wrote:
@kovdan01 Thank you for the reproducer!
I restored the original check `TI->readsRegister(AArch64::X16, TRI) ?
AArch64::X17 : AArch64::X16` when computing the scratch register, as checking
just the specific operand did not handle the `AUTH_TCRETURN*` pseudos which
actually h
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110705
>From 089cc13bbd2cac76a2d3fc0b2f72b0bccda5b188 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 23 Sep 2024 19:51:55 +0300
Subject: [PATCH 1/2] [AArch64][PAC] Move emission of LR checks in tail c
atrosinenko wrote:
Updated the commit message: removed the paragraph about dropping one `mov`
instruction from the non-trapping variant of check. That was my initial idea to
make non-hint `xpac(i|d)` operate on the tested register itself (just like
`xpaclri` does), but it was removed from the
https://github.com/atrosinenko edited
https://github.com/llvm/llvm-project/pull/110705
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https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110705
>From 089cc13bbd2cac76a2d3fc0b2f72b0bccda5b188 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 23 Sep 2024 19:51:55 +0300
Subject: [PATCH] [AArch64][PAC] Move emission of LR checks in tail calls
atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110705?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/atrosinenko ready_for_review
https://github.com/llvm/llvm-project/pull/110705
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https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/110705
Move the emission of the checks performed on the authenticated LR value
during tail calls to AArch64AsmPrinter class, so that different checker
sequences can be reused by pseudo instructions expanded there.
T
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110108
>From 92eb911fcd781825fa88aaec6c05b9484f49d158 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 25 Sep 2024 16:16:29 +0300
Subject: [PATCH] [AArch64] Generalize the instruction size checking in
atrosinenko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110108?utm_source=stack-comment-downstack-mergeability-warni
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110108
>From af03c2af4aedd58ab941250d19c965ad774c4a46 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 25 Sep 2024 16:16:29 +0300
Subject: [PATCH] [AArch64] Generalize the instruction size checking in
atrosinenko wrote:
Thank you for the review!
> As you are adding a new function, it's good time to fix the naming case to
> `emitToStreamer`
I think renaming `EmitToStreamer` to `emitToStreamer` now may be a bit
error-prone, as this function overrides the non-virtual
`AsmPrinter::EmitToStrea
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/110108
Most of PAuth-related code counts the instructions being inserted and asserts
that no more bytes are emitted than the size returned by the
getInstSizeInBytes(MI) method. This check seems useful not only for
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/110107
In preparation for refactoring the instruction size checks being made by
PAuth-related code, switch all instruction emission in AArch64AsmPrinter to
using EmitToStreamer function.
Introduce a single-operan
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From 84e7eb3c36b99ac7f673d9a7ad0c88c469f7f45d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH 1/2] [AArch64][PAC] Support BLRA* instructions in SLS
Har
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From 84e7eb3c36b99ac7f673d9a7ad0c88c469f7f45d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH] [AArch64][PAC] Support BLRA* instructions in SLS Hardenin
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From f49c32c8465e9e68d7345fa82ae1294cc2faf0e7 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH] [AArch64][PAC] Support BLRA* instructions in SLS Hardenin
@@ -36,38 +32,43 @@ using namespace llvm;
#define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
+static const char SLSBLRNamePrefix[] = "__llvm_slsblr_thunk_";
+
namespace {
-class AArch64SLSHardening : public MachineFunctionPass {
-public:
- const TargetInstrIn
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/97605
Make SLS Hardening pass handle BLRA* instructions the same way it handles BLR.
The thunk names have the form
__llvm_slsblr_thunk_xNfor BLR thunks
__llvm_slsblr_thunk_(aaz|abz)_xN for BLR
https://github.com/atrosinenko edited
https://github.com/llvm/llvm-project/pull/97472
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https://github.com/atrosinenko edited
https://github.com/llvm/llvm-project/pull/97472
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https://github.com/atrosinenko commented:
@kbeyls thank you for the comments!
https://github.com/llvm/llvm-project/pull/97472
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@@ -36,38 +32,43 @@ using namespace llvm;
#define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
+static const char SLSBLRNamePrefix[] = "__llvm_slsblr_thunk_";
+
namespace {
-class AArch64SLSHardening : public MachineFunctionPass {
-public:
- const TargetInstrIn
@@ -46,13 +40,5 @@ body: |
...
-name:__llvm_slsblr_thunk_x8
-tracksRegLiveness: true
-body: |
- bb.0.entry:
-liveins: $x8
-BR $x8
atrosinenko wrote:
The above lines are **input** to `llc`, so I removed them
@@ -36,38 +32,43 @@ using namespace llvm;
#define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
+static const char SLSBLRNamePrefix[] = "__llvm_slsblr_thunk_";
+
namespace {
-class AArch64SLSHardening : public MachineFunctionPass {
-public:
- const TargetInstrIn
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97472
>From a246cfe705b326c520d6b36882a17bd90b622e5d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Fri, 28 Jun 2024 21:50:24 +0300
Subject: [PATCH 1/2] [AArch64] Only create called thunks when hardening
https://github.com/atrosinenko created
https://github.com/llvm/llvm-project/pull/97472
In preparation for implementing hardening of BLRA* instructions, restrict thunk
function generation to only the thunks being actually called from any function.
As described in the existing comments, emitting
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