shiltian wrote:
Even after I expanded all folded files, when I search for `__kmpc_parallel_60`,
my browser only shows three matches. Did I miss anything here?
https://github.com/llvm/llvm-project/pull/146405
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https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/146404
>From cf566c60db9eef81c39a45082645c9d44992bec5 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler
Date: Fri, 27 Jun 2025 07:54:07 -0500
Subject: [PATCH 1/2] [OpenMP][clang] 6.0: num_threads strict (part 2: device
ru
@@ -45,7 +45,24 @@ using namespace ompx;
namespace {
-uint32_t determineNumberOfThreads(int32_t NumThreadsClause) {
+void num_threads_strict_error(int32_t nt_strict, int32_t nt_severity,
ro-i wrote:
sorry, done
https://github.com/llvm/llvm-project/pull/1464
@@ -45,7 +45,24 @@ using namespace ompx;
namespace {
-uint32_t determineNumberOfThreads(int32_t NumThreadsClause) {
+void num_threads_strict_error(int32_t nt_strict, int32_t nt_severity,
shiltian wrote:
Please use LLVM code style for device runtime.
https:/
https://github.com/shiltian commented:
There doesn't seem to be any test case for the new added `__kmpc_parallel_60`.
If it is orthogonal to the `__kmpc_push_num_threads_strict` change, I'd prefer
to make it a separate PR and have tests there.
https://github.com/llvm/llvm-project/pull/146405
_
llvmbot wrote:
@llvm/pr-subscribers-offload
Author: Robert Imschweiler (ro-i)
Changes
OpenMP 6.0 12.1.2 specifies the behavior of the strict modifier for the
num_threads clause on parallel directives, along with the message and severity
clauses. This commit implements necessary device ru
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: Robert Imschweiler (ro-i)
Changes
OpenMP 6.0 12.1.2 specifies the behavior of the strict modifier for the
num_threads clause on parallel directives, along with the message and severity
clauses. This commit implements necessary cod
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Robert Imschweiler (ro-i)
Changes
OpenMP 6.0 12.1.2 specifies the behavior of the strict modifier for the
num_threads clause on parallel directives, along with the message and severity
clauses. This commit implements necessary codegen cha
https://github.com/ro-i created https://github.com/llvm/llvm-project/pull/146404
OpenMP 6.0 12.1.2 specifies the behavior of the strict modifier for the
num_threads clause on parallel directives, along with the message and severity
clauses. This commit implements necessary device runtime change
https://github.com/evelez7 updated
https://github.com/llvm/llvm-project/pull/146165
>From 318f0c85b9f984ba22873ee76a0e610b07d443e9 Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Thu, 26 Jun 2025 20:54:03 -0700
Subject: [PATCH] [clang-doc] serialize friends
---
clang-tools-extra/clang-doc/Bi
https://github.com/evelez7 updated
https://github.com/llvm/llvm-project/pull/146165
>From 318f0c85b9f984ba22873ee76a0e610b07d443e9 Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Thu, 26 Jun 2025 20:54:03 -0700
Subject: [PATCH] [clang-doc] serialize friends
---
clang-tools-extra/clang-doc/Bi
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/146329
>From 69c97078a3e7ee1592e5e5c4b2f4eba6455dd96e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 25 Jun 2025 21:22:43 +0100
Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/146329
>From 69c97078a3e7ee1592e5e5c4b2f4eba6455dd96e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 25 Jun 2025 21:22:43 +0100
Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Erick Velez (evelez7)
Changes
---
Patch is 24.39 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/146165.diff
13 Files Affected:
- (modified) clang-tools-extra/clang-doc/BitcodeRe
https://github.com/evelez7 ready_for_review
https://github.com/llvm/llvm-project/pull/146165
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@@ -1,115 +1,203 @@
-// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s
--check-prefix=NO-GCS
-// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t
+// RUN: llvm-mc -triple=aarch
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/146331
>From 8c9eccdc95e465fdbfe833080afb1ad1099c224c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 27 Jun 2025 20:16:06 +0100
Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file
@@ -16,28 +16,41 @@
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,-clrbhb
< %s | FileCheck %s --check-prefix=HINT_22
// Optional, off by default, manually enabled
-// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s |
FileCheck
@@ -1,592 +1,697 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding
-mattr=+the -mattr=+d128 < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding
-mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s
-// RUN
@@ -1,55 +1,117 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s
| FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck
--check-prefix=CHECK-NO-MEC %s
-
- mrs x0, MECIDR_EL2
-// CHECK: mrs x0, MECIDR_
@@ -0,0 +1,138 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:| FileCheck %s --check-prefixes=CHECK-E
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/146329
>From be8bcdead883ec9bac8bebf6b3382974fc988c28 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 25 Jun 2025 21:22:43 +0100
Subject: [PATCH 1/2] [AArch64][llvm] Unify AArch64 tests into a single file
https://github.com/ritter-x2a edited
https://github.com/llvm/llvm-project/pull/146075
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@@ -416,6 +416,60 @@ entry:
ret void
}
+; Check that ptradds can be lowered to disjoint ORs.
+define ptr @gep_disjoint_or(ptr %base) {
+; GFX942-LABEL: gep_disjoint_or:
+; GFX942: ; %bb.0:
+; GFX942-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:v_
@@ -15136,6 +15136,41 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode
*N,
return Folded;
}
+ // Transform (ptradd a, b) -> (or disjoint a, b) if it is equivalent and if
+ // that transformation can't block an offset folding at any use of the
ptradd.
+ //
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 452008111a34c815b38242272063654393261921 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 2d8d232729769a3ca274789dee2fe542d0045ef2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default
A
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 2d8d232729769a3ca274789dee2fe542d0045ef2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default
A
https://github.com/AaronBallman approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/146155
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https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/146343
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llvmbot wrote:
@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-webassembly
Author: Matt Arsenault (arsenm)
Changes
Currently wasm adds an extra level of options that work backwards
from the standard options, and overwrites them. The ExceptionModel
field in TM->Options is the
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146343?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146343
Currently wasm adds an extra level of options that work backwards
from the standard options, and overwrites them. The ExceptionModel
field in TM->Options is the standard user configuration option for the
exception
shiltian wrote:
### Merge activity
* **Jun 30, 11:47 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/146305).
https://github.com/llvm/llvm-project/pull/146305
__
@@ -1,592 +1,697 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding
-mattr=+the -mattr=+d128 < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding
-mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s
-// RUN
@@ -16,28 +16,41 @@
// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,-clrbhb
< %s | FileCheck %s --check-prefix=HINT_22
// Optional, off by default, manually enabled
-// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s |
FileCheck
@@ -0,0 +1,138 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:| FileCheck %s --check-prefixes=CHECK-E
@@ -1,115 +1,203 @@
-// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s
--check-prefix=NO-GCS
-// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t
+// RUN: llvm-mc -triple=aarch
@@ -1,55 +1,117 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s
| FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck
--check-prefix=CHECK-NO-MEC %s
-
- mrs x0, MECIDR_EL2
-// CHECK: mrs x0, MECIDR_
@@ -297,8 +297,13 @@ namespace CallingConv {
/// directly or indirectly via a call-like instruction.
constexpr bool isCallableCC(CallingConv::ID CC) {
switch (CC) {
+ // Called with special intrinsics:
+ // llvm.amdgcn.cs.chain
case CallingConv::AMDGPU_CS_Chain:
case
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/146330
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https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/146331
This is a series of patches (4/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instructions and system registers are thoroughly test
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/146330
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Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/141589
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llvmbot wrote:
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
Changes
This is a series of patches (4/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instruction
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Jonathan Thackray (jthackray)
Changes
This is a series of patches (3/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instructions and system registers are thoroughly
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
Changes
This is a series of patches (3/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instructions and system registers a
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
Changes
This is a series of patches (2/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instructions and system registers a
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/146329
This is a series of patches (2/4) to unify assembly/disassembly of recent
AArch64 tests into a single file. The aim is to improve consistency, so that
all instructions and system registers are thoroughly test
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/145484
>From b031681978e2b356c2ae8e65d6e08515c0044ac1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 24 Jun 2025 11:35:58 +0200
Subject: [PATCH 1/2] [AMDGPU] Use reverse iteration in CodeGenPrepare
In order to m
@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010
-new-reg-bank-select < %s | FileCheck %s
+
+define amdgpu_ps void @readanylane_to_virtual_vgpr
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (R
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 7c5c7bf98afe91f015b36e42536a8a700b27b686 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 7c5c7bf98afe91f015b36e42536a8a700b27b686 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 046418f7ccd46a2b0c2ea3c9ab15e659de709b27 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 26615132899d40b8d245fd98d093ef8c26cdc3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From d97992ef24abae69878fd1e49270bf0f7372ca39 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From f137136b2f527aaf1b2f2847e821085aabfc299e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 26615132899d40b8d245fd98d093ef8c26cdc3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From f137136b2f527aaf1b2f2847e821085aabfc299e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From d97992ef24abae69878fd1e49270bf0f7372ca39 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
jayfoad wrote:
Does this also handle the case where _all_ of the values ORed together are
shifted, like `(setcc ((x >> c0 | x >> c1 | ...) & mask))` ?
https://github.com/llvm/llvm-project/pull/146054
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@@ -140,3 +140,92 @@ bool CombinerHelper::matchCanonicalizeFCmp(const
MachineInstr &MI,
return false;
}
+
+bool CombinerHelper::combineMergedBFXCompare(MachineInstr &MI) const {
+ const GICmp *Cmp = cast(&MI);
+
+ ICmpInst::Predicate CC = Cmp->getCond();
+ if (CC != CmpI
@@ -28909,13 +28909,99 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (R
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 17ac90ad1ee167f35321e01625a207f2b94ff523 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From da05cc2d920917f0cb6f171b0d9e2e535836ca3c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146053
>From 3f62ab3beb30abbf8c8c32dd79c0133f7ca122e0 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH 1/2] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimizati
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146054
>From 17ac90ad1ee167f35321e01625a207f2b94ff523 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:31:37 +0200
Subject: [PATCH 1/2] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences
Fold
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/146055
>From da05cc2d920917f0cb6f171b0d9e2e535836ca3c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 27 Jun 2025 12:04:53 +0200
Subject: [PATCH] [GISel] Combine compare of bitfield extracts or'd together.
Equiva
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern suc
https://github.com/zero9178 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/146243
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Pierre-vh wrote:
> Why DAG and not InstCombine for this?
The intrinsics we want to optimize with this aren't lowered yet at IC
https://github.com/llvm/llvm-project/pull/146054
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