[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/145197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/145197 >From dfe7d53af6927c28dd0155c0c330013d466af495 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sun, 22 Jun 2025 09:12:19 +0900 Subject: [PATCH] DAG: Emit an error if trying to legalize read/write register wi

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/145197.diff 5 Files Affected: - (modified) llvm/include/llvm/IR/DiagnosticInfo.h (+25) - (modified) llvm/lib/CodeGen/SelectionDAG/Legal

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

@@ -636,5 +636,11 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi", "nc", "bitop3-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc", "f32-to-f16bf16-cvt-sr-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc", "f32-to-

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N support to `replaceUsesOfBlockArgument` (PR #145171)

https://github.com/j2kun approved this pull request. https://github.com/llvm/llvm-project/pull/145171 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

llvmbot wrote: @llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-mips Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/145197.diff 5 Files Affected: - (modified) llvm/include/llvm/IR/DiagnosticInfo.h (+25) - (modified) l

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

llvmbot wrote: @llvm/pr-subscribers-backend-powerpc Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/145197.diff 5 Files Affected: - (modified) llvm/include/llvm/IR/DiagnosticInfo.h (+25) - (modified) llvm/lib/CodeGen/SelectionDAG/Legal

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145197?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] DAG: Emit an error if trying to legalize read/write register with illegal types (PR #145197)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/145197 None >From 4c1a7fc9c8a546b7d8d0eb52bbad4ddae85598ee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sun, 22 Jun 2025 09:12:19 +0900 Subject: [PATCH] DAG: Emit an error if trying to legalize read/write regist

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX1250 %s rampitec wrote: Will do. This is a very old

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); + if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts()) rampitec wrote: 0x means it is already a real opcode. 0x means it is n

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N support to `replaceUsesOfBlockArgument` (PR #145171)

@@ -1434,12 +1439,15 @@ Block *ConversionPatternRewriterImpl::applySignatureConversion( if (!inputMap) { // This block argument was dropped and no replacement value was provided. // Materialize a replacement value "out of thin air". - buildUnresolvedMateri

[llvm-branch-commits] [llvm] cd646d1 - Revert "[ValueTracking] Improve `Bitcast` handling to match SDAG (#125935)"

Author: Arthur Eubanks Date: 2025-06-21T15:19:21-07:00 New Revision: cd646d16794e787b58c4e0a632483876f0952198 URL: https://github.com/llvm/llvm-project/commit/cd646d16794e787b58c4e0a632483876f0952198 DIFF: https://github.com/llvm/llvm-project/commit/cd646d16794e787b58c4e0a632483876f0952198.diff

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N support to `replaceUsesOfBlockArgument` (PR #145171)

llvmbot wrote: @llvm/pr-subscribers-mlir Author: Matthias Springer (matthias-springer) Changes This commit adds 1:N support to `ConversionPatternRewriter::replaceUsesOfBlockArgument`. This was one of the few remaining dialect conversion APIs that does not support 1:N conversions yet. Th

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX1250 %s shiltian wrote: I think it is recommended to

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N support to `replaceUsesOfBlockArgument` (PR #145171)

llvmbot wrote: @llvm/pr-subscribers-mlir-core Author: Matthias Springer (matthias-springer) Changes This commit adds 1:N support to `ConversionPatternRewriter::replaceUsesOfBlockArgument`. This was one of the few remaining dialect conversion APIs that does not support 1:N conversions yet

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N support to `replaceUsesOfBlockArgument` (PR #145171)

https://github.com/matthias-springer created https://github.com/llvm/llvm-project/pull/145171 This commit adds 1:N support to `ConversionPatternRewriter::replaceUsesOfBlockArgument`. This was one of the few remaining dialect conversion APIs that does not support 1:N conversions yet. This comm

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); + if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts()) shiltian wrote: So we want a `0x` instead of a `0x` here? Why is that?

[llvm-branch-commits] [llvm-objdump] Support --symbolize-operand on AArch64 (PR #145009)

https://github.com/MaskRay commented: Looks good, but I'd check whether @jh7370 has opinions on the test. (We need an executable for testing. llvm/test cannot use lld, so we have to resort to hexadecimal bytes...) https://github.com/llvm/llvm-project/pull/145009

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/145152 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libcxx] 7fd7f52 - Revert "[libc++] Simplify a bit (#140021)"

Author: Nikolas Klauser Date: 2025-06-21T09:58:49+02:00 New Revision: 7fd7f5272034a6bb5987660a8b764842c62d18d5 URL: https://github.com/llvm/llvm-project/commit/7fd7f5272034a6bb5987660a8b764842c62d18d5 DIFF: https://github.com/llvm/llvm-project/commit/7fd7f5272034a6bb5987660a8b764842c62d18d5.dif

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

rampitec wrote: Actually the first codegen test for the subtarget. https://github.com/llvm/llvm-project/pull/145152 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-comm

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

llvmbot wrote: @llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-amdgpu Author: Stanislav Mekhanoshin (rampitec) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/145152.diff 12 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsAMDGPU.def (+6) - (add

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/145152 None >From ae162ef51dd115f68c86cce893a0ae7baf99e6b9 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri, 20 Jun 2025 12:24:47 -0700 Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction