llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
The darwinHasSinCos wasn't actually used for sincos, only the stret
variant. Rename this to reflect that, and introduce a new one for
enabling sincos.
---
Full diff: https://github.com/llvm/llvm-project/pu
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/143082.diff
2 Files Affected:
- (modified) llvm/include/llvm/IR/RuntimeLibcalls.h (+5-3)
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (-10)
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/143081
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https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/143082
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143082?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/143082
None
>From 8aa7850d9ddd50d57c9d9fbbef07b9ad00ffe202 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 6 Jun 2025 14:50:57 +0900
Subject: [PATCH] RuntimeLibcalls: Use array initializers for default values
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143081?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/143081
The darwinHasSinCos wasn't actually used for sincos, only the stret
variant. Rename this to reflect that, and introduce a new one for
enabling sincos.
>From ee79ca11029ca60e9b6062cde3d0f468c2d5a7b3 Mon Sep 17 00:
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/142905
>From a3cb3a4361182158b16e85952309c2ebbe9dfb32 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 5 Jun 2025 14:22:55 +0900
Subject: [PATCH] DAG: Move soft float predicate management into
RuntimeLibcalls
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/143054
Construct RuntimeLibcallsInfo instead of manually creating a map.
This was repeating the setting of the RETURN_ADDRESS. This removes
an obstacle to generating libcall information with tablegen.
This is also not g
llvmbot wrote:
@llvm/pr-subscribers-backend-webassembly
Author: Matt Arsenault (arsenm)
Changes
Construct RuntimeLibcallsInfo instead of manually creating a map.
This was repeating the setting of the RETURN_ADDRESS. This removes
an obstacle to generating libcall information with tablegen.
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/143054
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143054?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/fmayer commented:
Could we have a test that demonstrates the new better instruction sequence (by
precommiting to show the diff here)?
https://github.com/llvm/llvm-project/pull/142887
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/142912
>From f8721bd055a0fb775543df2059d0979d9c3487de Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 5 Jun 2025 16:08:26 +0900
Subject: [PATCH] CodeGen: Move ABI option enums to support
Move these out of Targ
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/142905
>From a3cb3a4361182158b16e85952309c2ebbe9dfb32 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 5 Jun 2025 14:22:55 +0900
Subject: [PATCH] DAG: Move soft float predicate management into
RuntimeLibcalls
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/142912
>From f8721bd055a0fb775543df2059d0979d9c3487de Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 5 Jun 2025 16:08:26 +0900
Subject: [PATCH] CodeGen: Move ABI option enums to support
Move these out of Targ
https://github.com/aaupov edited
https://github.com/llvm/llvm-project/pull/141674
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@@ -203,21 +206,21 @@ func.func @transfer_read_dynamic_dim_to_flatten(
return %res : vector<1x2x6xi32>
}
-// CHECK: #[[$MAP:.*]] = affine_map<()[s0, s1] -> (s0 * 24 + s1 * 6)>
+// CHECK: #[[$MAP:.+]] = affine_map<()[s0, s1] -> (s0 * 24 + s1 * 6)>
// CHECK-LABEL: func.func
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -630,7 +639,10 @@ class FlattenContiguousRowMajorTransferReadPattern
if (transferReadOp.getMask())
return failure();
-int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank();
newling wrote:
Why does this need to change?
If
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -582,6 +582,15 @@ static SmallVector getCollapsedIndices(RewriterBase
&rewriter,
namespace {
+/// Helper functon to return the index of the last dynamic dimension in
`shape`.
newling wrote:
```suggestion
/// Helper functon to return the index of the las
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
https://github.com/newling edited
https://github.com/llvm/llvm-project/pull/142422
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https://github.com/newling commented:
Thanks! Other than my question about the change to first dimension of the
memref that gets collapsed, my comments are all quite minor.
https://github.com/llvm/llvm-project/pull/142422
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https://github.com/kparzysz reopened
https://github.com/llvm/llvm-project/pull/141772
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@@ -11,12 +11,48 @@
using namespace llvm;
using namespace RTLIB;
+void RuntimeLibcallsInfo::initSoftFloatCmpLibcallPredicates() {
+ std::fill(SoftFloatCompareLibcallPredicates,
topperc wrote:
Should we be using `std::begin(SoftFloatCompareLibcallPredicates)`
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/142886
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https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/142886
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https://github.com/kparzysz closed
https://github.com/llvm/llvm-project/pull/141772
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https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/141327
>From b36c74c344ed47b99e9bfdc28f9081c3c704d8c7 Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Tue, 27 May 2025 23:08:59 -0700
Subject: [PATCH] Format
Created using spr 1.3.6-beta.1
---
llvm/lib/Transforms
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/141327
>From b36c74c344ed47b99e9bfdc28f9081c3c704d8c7 Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Tue, 27 May 2025 23:08:59 -0700
Subject: [PATCH] Format
Created using spr 1.3.6-beta.1
---
llvm/lib/Transforms
@@ -102,51 +102,25 @@ if [[ "${runtimes}" != "" ]]; then
exit 1
fi
- echo "--- ninja install-clang"
-
- ninja -C ${BUILD_DIR} install-clang install-clang-resource-headers
-
- RUNTIMES_BUILD_DIR="${MONOREPO_ROOT}/build-runtimes"
- INSTALL_DIR="${BUILD_DIR}/install"
-
https://github.com/bhandarkar-pranav updated
https://github.com/llvm/llvm-project/pull/141715
>From 2d411fc5d24c7e3e933447307fc958b7e544490b Mon Sep 17 00:00:00 2001
From: Pranav Bhandarkar
Date: Fri, 23 May 2025 10:26:14 -0500
Subject: [PATCH 1/5] Fix boxchar with firstprivate
---
.../Optimi
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 8f9a4002820dcd3de2a5986d53749386a2507eab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/4] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 8f9a4002820dcd3de2a5986d53749386a2507eab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/4] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/teresajohnson approved this pull request.
lgtm but I think there is a code formatting error reported that should be fixed
before merging.
https://github.com/llvm/llvm-project/pull/141327
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https://github.com/philnik777 approved this pull request.
LGTM with added comment.
https://github.com/llvm/llvm-project/pull/142925
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https://github.com/philnik777 edited
https://github.com/llvm/llvm-project/pull/142925
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@@ -451,6 +451,7 @@ namespace std {
# if _LIBCPP_STD_VER >= 23
#include <__fwd/mdspan.h>
+#include <__fwd/span.h>
philnik777 wrote:
Can you add a comment with the LWG issue number? If the answer is that we
indeed expect users to include `` we should
@@ -0,0 +1,24 @@
+;; Test if the callee_type metadata attached to indirect call sites adhere to
the expected format.
+
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+define i32 @_Z13call_indirectPFicEc(ptr %func, i8 signext %x) !type !0 {
+entry:
+ %func.addr = alloca ptr, alig
@@ -1302,6 +1302,24 @@ static void addRange(SmallVectorImpl
&EndPoints,
EndPoints.push_back(High);
}
+MDNode *MDNode::getMergedCalleeTypeMetadata(LLVMContext &Ctx, MDNode *A,
+MDNode *B) {
+ SmallVector AB;
+ SmallSet MergedCall
nikic wrote:
The way FileCheck works this will pass even if the metadata is not dropped. You
could try whether `FileCheck --match-full-lines` works. Otherwise you could use
explicit `CHECK-NOT` or `{{$}}`.
https://github.com/llvm/llvm-project/pull/87573
_
@@ -4161,6 +4161,11 @@ Instruction *InstCombinerImpl::visitCallBase(CallBase
&Call) {
Call, Builder.CreateBitOrPointerCast(ReturnedArg, CallTy));
}
+ // Drop unnecessary callee_type metadata from calls that were converted
+ // into direct calls.
+ if (Call.
@@ -3377,6 +3377,11 @@ static void combineMetadata(Instruction *K, const
Instruction *J,
K->setMetadata(Kind,
MDNode::getMostGenericAlignmentOrDereferenceable(JMD, KMD));
break;
+ case LLVMContext::MD_callee_type:
+if (!AAOnly)
+
@@ -5096,6 +5097,19 @@ void Verifier::visitCallsiteMetadata(Instruction &I,
MDNode *MD) {
visitCallStackMetadata(MD);
}
+void Verifier::visitCalleeTypeMetadata(Instruction &I, MDNode *MD) {
+ Check(isa(I), "!callee_type metadata should only exist on calls",
+&I);
+
@@ -1302,6 +1302,24 @@ static void addRange(SmallVectorImpl
&EndPoints,
EndPoints.push_back(High);
}
+MDNode *MDNode::getMergedCalleeTypeMetadata(LLVMContext &Ctx, MDNode *A,
+MDNode *B) {
+ SmallVector AB;
+ SmallSet MergedCall
@@ -1252,6 +1252,12 @@ class MDNode : public Metadata {
bool isReplaceable() const { return isTemporary() || isAlwaysReplaceable(); }
bool isAlwaysReplaceable() const { return getMetadataID() == DIAssignIDKind;
}
+ bool hasGeneralizedMDString() const {
n
@@ -1302,6 +1302,24 @@ static void addRange(SmallVectorImpl
&EndPoints,
EndPoints.push_back(High);
}
+MDNode *MDNode::getMergedCalleeTypeMetadata(LLVMContext &Ctx, MDNode *A,
+MDNode *B) {
+ SmallVector AB;
+ SmallSet MergedCall
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 2eb6c95955dc22b6b59eb4e5ba269e4744bbdd2a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
@@ -49,8 +49,7 @@
},
"lld": {"bolt", "cross-project-tests"},
# TODO(issues/132795): LLDB should be enabled on clang changes.
-"clang": {"clang-tools-extra", "compiler-rt", "cross-project-tests"},
-"clang-tools-extra": {"libc"},
Endilll wrote
https://github.com/Endilll approved this pull request.
https://github.com/llvm/llvm-project/pull/142694
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 2eb6c95955dc22b6b59eb4e5ba269e4744bbdd2a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -165,6 +165,8 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
// Src only modifiers: waterfalls, extends
+ Sgpr32_W,
+ SgprV4S32_W,
petar-avramovic wrote:
Added one above, is it clear now?
https://github.com/llvm/llvm-project/pull/142790
___
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ae9621601118004cc6b363be7fad70092e401cad Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ae9621601118004cc6b363be7fad70092e401cad Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 64d7853a9edefabe8de40748e01348d2d5c017c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 64d7853a9edefabe8de40748e01348d2d5c017c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
https://github.com/anutosh491 converted_to_draft
https://github.com/llvm/llvm-project/pull/142909
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anutosh491 wrote:
See https://github.com/llvm/llvm-project/pull/142933#issuecomment-2943354247 :(
https://github.com/llvm/llvm-project/pull/142909
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@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
https://github.com/nikic approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/142886
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@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
boomanaiden154 wrote:
Branch seems to be cleaned up now.
https://github.com/llvm/llvm-project/pull/142694
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boomanaiden154 wrote:
> Multiconfig in this context has some strong associations with CMake's Ninja
> Multi-Config generator for me. My suggestion is needs_reconfig.
> Agree with needs_reconfig.
Updated. Thanks for the suggestion!
https://github.com/llvm/llvm-project/pull/142696
_
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/142696
>From 360e723b51ee201603f72b56859cd7c6d6faec24 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Thu, 5 Jun 2025 06:51:37 +
Subject: [PATCH 1/2] feedback
Created using spr 1.3.4
---
.ci/compute_pr
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -894,6 +1121,15 @@ void RegBankLegalizeHelper::applyMappingSrc(
}
break;
}
+// sgpr waterfall, scalars and vectors
+case Sgpr32_W:
+case SgprV4S32_W: {
+ assert(Ty == getTyFromID(MethodIDs[i]));
+ if (RB != SgprRB) {
+SgprWaterfa
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -165,6 +165,8 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
// Src only modifiers: waterfalls, extends
+ Sgpr32_W,
+ SgprV4S32_W,
Pierre-vh wrote:
Can you add a trailing comment or rename this ? The `_W` suffix is not
immediately clear to me
http
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect
-regbankselect-fast -o - %s | FileCheck %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-afte
@@ -117,45 +117,73 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
+typedef std::functionhttps://github.com/llvm/l
@@ -117,45 +117,73 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
+typedef std::function
+ReadLaneFnTy;
+
+st
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
Pierre-vh wrote:
```suggestion
std::pair tryMatchRALFromUnmerge(Register Src) {
```
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
Pierre-vh wrote:
```suggestion
Machin
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
Endilll wrote:
> > It doesn't relate to multilib, I understand that, but does it mean we're
> > going to test more than one runtime or that we'll test the same runtime
> > multiple ways?
>
> It's runtimes that we test in multiple ways (`-std=c++26` and
> `enable_modules=clang` currently). I f
@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
boomanaiden154 wrote:
> There's still an outstanding question of unrelated changes to libc++ tests
> that are included in this PR.
I'm still not sure how they're ending up in here. I haven't seen this before
with `spr`. This will definitely be fixed before I end up landing the patch and
I'm g
https://github.com/Endilll commented:
> We're using LLVM_ENABLE_RUNTIMES. It uses the just built clang to build the
> runtimes specified.
That explains it, thank you.
There's still an outstanding question of unrelated changes to libc++ tests that
are included in this PR.
https://github.com/ll
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/142911
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/142910
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@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
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