[llvm-branch-commits] [llvm] [DirectX] Update resource type names in DXIL metadata to include element type (PR #140937)

2025-05-22 Thread Helena Kotas via llvm-branch-commits
https://github.com/hekota updated https://github.com/llvm/llvm-project/pull/140937 >From 3f882eb22c0035e5f9dfe7b7324fb44a7a66dea8 Mon Sep 17 00:00:00 2001 From: Helena Kotas Date: Wed, 21 May 2025 09:18:02 -0700 Subject: [PATCH 1/4] [DirectX] Update resource type names in DXIL metadata to incl

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/138366 >From 03060849dc81f83ec48f05995ac8fd6df846c25b Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Fri, 2 May 2025 16:57:28 -0700 Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?U

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/138366 >From e0581c892d07d8bb5518fa412b75b8830f5fb14a Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Wed, 30 Apr 2025 18:25:54 -0700 Subject: [PATCH] ELF: Add branch-to-branch optimization. MIME-Version: 1.0 Conte

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
@@ -0,0 +1,92 @@ +//===- TargetImpl.h -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
@@ -0,0 +1,92 @@ +//===- TargetImpl.h -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
@@ -975,6 +977,62 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { } } +static std::optional getControlTransferAddend(InputSection &is, +Relocation &r) { + // Identify a control transfer rel

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
@@ -0,0 +1,92 @@ +//===- TargetImpl.h -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
https://github.com/pcc edited https://github.com/llvm/llvm-project/pull/138366 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] ELF: Add branch-to-branch optimization. (PR #138366)

2025-05-22 Thread Peter Collingbourne via llvm-branch-commits
https://github.com/pcc edited https://github.com/llvm/llvm-project/pull/138366 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Fix assertion failure for annotate tablejump (#140907) (PR #141193)

2025-05-22 Thread via llvm-branch-commits
llvmbot wrote: @wangleiat What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/141193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/lis

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Fix assertion failure for annotate tablejump (#140907) (PR #141193)

2025-05-22 Thread via llvm-branch-commits
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/141193 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [LoongArch] Fix assertion failure for annotate tablejump (#140907) (PR #141193)

2025-05-22 Thread via llvm-branch-commits
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/141193 Backport 4e186f20e2f2be2fbf95d9713341a0b6507e707d Requested by: @heiher >From bc2bfeef77ad84512cec890f65944e46298dbd6c Mon Sep 17 00:00:00 2001 From: hev Date: Thu, 22 May 2025 18:50:40 +0800 Subject: [PATCH]

[llvm-branch-commits] [llvm] [NFC] Updating RTS0 namespace to contain all elements related to it's representation (PR #141173)

2025-05-22 Thread Finn Plummer via llvm-branch-commits
https://github.com/inbelic approved this pull request. Ha the diff confused me, the diff makes it look like `RootDescriptor` is moving namespaces but in reality it is all the ones in between that are changing. https://github.com/llvm/llvm-project/pull/141173

[llvm-branch-commits] [llvm] [DirectX] adding support to read/write descriptor table data using obj2yaml/yaml2obj (PR #138315)

2025-05-22 Thread via llvm-branch-commits
https://github.com/joaosaffran ready_for_review https://github.com/llvm/llvm-project/pull/138315 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [DirectX] adding support to read/write descriptor table data using obj2yaml/yaml2obj (PR #138315)

2025-05-22 Thread via llvm-branch-commits
https://github.com/joaosaffran edited https://github.com/llvm/llvm-project/pull/138315 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

2025-05-22 Thread via llvm-branch-commits
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 >From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 09:33:39 +0700 Subject: [PATCH] Rework isFPImmLegal Created using spr 1.3.5 --- llvm/lib/Target/Sparc

[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

2025-05-22 Thread via llvm-branch-commits
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 >From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 09:33:39 +0700 Subject: [PATCH] Rework isFPImmLegal Created using spr 1.3.5 --- llvm/lib/Target/Sparc

[llvm-branch-commits] [llvm] [NFC] Updating RTS0 namespace to contain all elements related to it's representation (PR #141173)

2025-05-22 Thread via llvm-branch-commits
llvmbot wrote: @llvm/pr-subscribers-mc Author: None (joaosaffran) Changes As requested in a previous PR, this change moves all structs related to RTS0 to RTS0 namespace. --- Full diff: https://github.com/llvm/llvm-project/pull/141173.diff 8 Files Affected: - (modified) llvm/include/ll

[llvm-branch-commits] [llvm] [NFC] Updating RTS0 namespace to contain all elements related to it's representation (PR #141173)

2025-05-22 Thread via llvm-branch-commits
llvmbot wrote: @llvm/pr-subscribers-backend-directx Author: None (joaosaffran) Changes As requested in a previous PR, this change moves all structs related to RTS0 to RTS0 namespace. --- Full diff: https://github.com/llvm/llvm-project/pull/141173.diff 8 Files Affected: - (modified) ll

[llvm-branch-commits] [llvm] [NFC] Updating RTS0 namespace to contain all elements related to it's representation (PR #141173)

2025-05-22 Thread via llvm-branch-commits
https://github.com/joaosaffran created https://github.com/llvm/llvm-project/pull/141173 As requested in a previous PR, this change moves all structs related to RTS0 to RTS0 namespace. >From e6553158dbfd718a2e9d76d6209cc3004abf Mon Sep 17 00:00:00 2001 From: joaosaffran Date: Fri, 23 May 2

[llvm-branch-commits] [llvm] 0c0257e - Revert "Revert "[StaticDataLayout][PGO]Implement reader and writer change for…"

2025-05-22 Thread via llvm-branch-commits
Author: Mingming Liu Date: 2025-05-22T17:22:16-07:00 New Revision: 0c0257e6243af40acf9ba1a86373398a202a533f URL: https://github.com/llvm/llvm-project/commit/0c0257e6243af40acf9ba1a86373398a202a533f DIFF: https://github.com/llvm/llvm-project/commit/0c0257e6243af40acf9ba1a86373398a202a533f.diff

[llvm-branch-commits] [clang] [KeyInstr][Clang] For stmt atom (PR #134646)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -1416,6 +1424,12 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, if (CGM.shouldEmitConvergenceTokens()) ConvergenceTokenStack.pop_back(); + + if (ForBody) { +// Key Instructions: We want the for closing brace to be step-able on to +// match existing be

[llvm-branch-commits] [clang] [KeyInstr][Clang] For stmt atom (PR #134646)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,37 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kind=line-tabl

[llvm-branch-commits] [clang] [KeyInstr][Clang] For stmt atom (PR #134646)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse commented: Question inline https://github.com/llvm/llvm-project/pull/134646 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] For stmt atom (PR #134646)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -1362,7 +1363,14 @@ void CodeGenFunction::EmitForStmt(const ForStmt &S, BoolCondVal = emitCondLikelihoodViaExpectIntrinsic( BoolCondVal, Stmt::getLikelihood(S.getBody())); -Builder.CreateCondBr(BoolCondVal, ForBody, ExitBlock, Weights); +auto *I = Bu

[llvm-branch-commits] [clang] [KeyInstr][Clang] For stmt atom (PR #134646)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse edited https://github.com/llvm/llvm-project/pull/134646 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] While stmt atom (PR #134645)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse approved this pull request. LGTM with nits https://github.com/llvm/llvm-project/pull/134645 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [clang] [KeyInstr][Clang] While stmt atom (PR #134645)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse edited https://github.com/llvm/llvm-project/pull/134645 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] While stmt atom (PR #134645)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kin

[llvm-branch-commits] [clang] [KeyInstr][Clang] While stmt atom (PR #134645)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kin

[llvm-branch-commits] [clang] [KeyInstr][Clang] While stmt atom (PR #134645)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -1130,7 +1130,14 @@ void CodeGenFunction::EmitWhileStmt(const WhileStmt &S, if (!Weights && CGM.getCodeGenOpts().OptimizationLevel) BoolCondVal = emitCondLikelihoodViaExpectIntrinsic( BoolCondVal, Stmt::getLikelihood(S.getBody())); -Builder.CreateCond

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -1242,9 +1242,17 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S, // As long as the condition is true, iterate the loop. if (EmitBoolCondBranch) { uint64_t BackedgeCount = getProfileCount(S.getBody()) - ParentCount; -Builder.CreateCondBr( +auto *I = Build

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse approved this pull request. LGTM with some nits to address. https://github.com/llvm/llvm-project/pull/134644 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listi

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse edited https://github.com/llvm/llvm-project/pull/134644 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -1242,9 +1242,17 @@ void CodeGenFunction::EmitDoStmt(const DoStmt &S, // As long as the condition is true, iterate the loop. if (EmitBoolCondBranch) { uint64_t BackedgeCount = getProfileCount(S.getBody()) - ParentCount; -Builder.CreateCondBr( +auto *I = Build

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,33 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kin

[llvm-branch-commits] [clang] [KeyInstr][Clang] Do stmt atom (PR #134644)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,33 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kin

[llvm-branch-commits] [llvm] f2479c4 - Revert "[StaticDataLayout][PGO]Implement reader and writer change for data ac…"

2025-05-22 Thread via llvm-branch-commits
Author: Mingming Liu Date: 2025-05-22T16:13:38-07:00 New Revision: f2479c4fb9e402e6a845eca455f744ad947d333f URL: https://github.com/llvm/llvm-project/commit/f2479c4fb9e402e6a845eca455f744ad947d333f DIFF: https://github.com/llvm/llvm-project/commit/f2479c4fb9e402e6a845eca455f744ad947d333f.diff

[llvm-branch-commits] [clang] [KeyInstr][Clang] Switch stmt atom (PR #134643)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,51 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank --check-prefixes=CHECK,CHECK-CXX + +// RUN: %clang_cc1 -gkey-inst

[llvm-branch-commits] [clang] [KeyInstr][Clang] Switch stmt atom (PR #134643)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse approved this pull request. LGTM with some test nits, please do disagree with those https://github.com/llvm/llvm-project/pull/134643 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.or

[llvm-branch-commits] [clang] [KeyInstr][Clang] Switch stmt atom (PR #134643)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
@@ -0,0 +1,51 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ -std=c++17 %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank --check-prefixes=CHECK,CHECK-CXX + +// RUN: %clang_cc1 -gkey-inst

[llvm-branch-commits] [clang] [KeyInstr][Clang] Switch stmt atom (PR #134643)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse edited https://github.com/llvm/llvm-project/pull/134643 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] If stmt atom (PR #134642)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/134642 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

2025-05-22 Thread via llvm-branch-commits
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 >From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 09:33:39 +0700 Subject: [PATCH] Rework isFPImmLegal Created using spr 1.3.5 --- llvm/lib/Target/Sparc

[llvm-branch-commits] [llvm] [SPARC] Use op-then-halve instructions when we have VIS3 (PR #135718)

2025-05-22 Thread via llvm-branch-commits
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/135718 >From 50422a4d24403ef55bf76ccd710511e8dec6b77d Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 09:33:39 +0700 Subject: [PATCH] Rework isFPImmLegal Created using spr 1.3.5 --- llvm/lib/Target/Sparc

[llvm-branch-commits] [llvm] [DirectX] adding support to read/write descriptor table data using obj2yaml/yaml2obj (PR #138315)

2025-05-22 Thread via llvm-branch-commits
https://github.com/joaosaffran edited https://github.com/llvm/llvm-project/pull/138315 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Implement setupTemplateValue for HTMLMustacheGenerator (PR #138064)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138064 >From 5e56a521547f6e5b309fcfd65f5ad459a03f9abc Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 08:13:46 -0700 Subject: [PATCH] [clang-doc] Implement setupTemplateValue for HTMLMustacheGenerator

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Update serializer for improved template handling (PR #138065)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138065 >From 2d48537e7a270c0a1c6f463ef1118a65c40a6f27 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 29 Apr 2025 18:31:54 -0700 Subject: [PATCH] [clang-doc] Update serializer for improved template handling This

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Extract Info into JSON values (PR #138063)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138063 >From 6880c2fcb571c53ad4e21804b805e82a93077bc1 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 08:11:39 -0700 Subject: [PATCH] [clang-doc] Extract Info into JSON values Split from #133161. This

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Update clang-doc tool to enable mustache templates (PR #138066)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138066 >From e94b231dbca9073da99f616516e21350d1136168 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 29 Apr 2025 18:08:03 -0700 Subject: [PATCH] [clang-doc] Update clang-doc tool to enable mustache templates Th

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Extract Info into JSON values (PR #138063)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138063 >From 6880c2fcb571c53ad4e21804b805e82a93077bc1 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 08:11:39 -0700 Subject: [PATCH] [clang-doc] Extract Info into JSON values Split from #133161. This

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Update serializer for improved template handling (PR #138065)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138065 >From 2d48537e7a270c0a1c6f463ef1118a65c40a6f27 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 29 Apr 2025 18:31:54 -0700 Subject: [PATCH] [clang-doc] Update serializer for improved template handling This

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Track if a type is a template or builtin (PR #138067)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138067 >From 46795349a75a0815041e7ac3038be9c00ce8ad2b Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 14:20:40 -0700 Subject: [PATCH] [clang-doc] Track if a type is a template or builtin Originally pa

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Implement setupTemplateValue for HTMLMustacheGenerator (PR #138064)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138064 >From 5e56a521547f6e5b309fcfd65f5ad459a03f9abc Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 08:13:46 -0700 Subject: [PATCH] [clang-doc] Implement setupTemplateValue for HTMLMustacheGenerator

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Update clang-doc tool to enable mustache templates (PR #138066)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138066 >From e94b231dbca9073da99f616516e21350d1136168 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 29 Apr 2025 18:08:03 -0700 Subject: [PATCH] [clang-doc] Update clang-doc tool to enable mustache templates Th

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Track if a type is a template or builtin (PR #138067)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138067 >From 46795349a75a0815041e7ac3038be9c00ce8ad2b Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 14:20:40 -0700 Subject: [PATCH] [clang-doc] Track if a type is a template or builtin Originally pa

[llvm-branch-commits] [clang] [clang] callee_type metadata for indirect calls (PR #117036)

2025-05-22 Thread Matt Arsenault via llvm-branch-commits
@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const NamedDecl *ND) { GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage); } +static bool hasExistingGeneralizedTypeMD(llvm::Function *F) { + llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext

[llvm-branch-commits] [llvm] [NFCI] Avoid adding duplicated SpecialCaseList::Sections. (PR #140821)

2025-05-22 Thread Qinkun Bao via llvm-branch-commits
qinkunbao wrote: Discussed with @vitalybuka offline. It turns out that Section name can be a regular expression so the order of Section needs to be tacked (with a vector). https://github.com/llvm/llvm-project/pull/140821 ___ llvm-branch-commits maili

[llvm-branch-commits] [llvm] [NFCI] Avoid adding duplicated SpecialCaseList::Sections. (PR #140821)

2025-05-22 Thread Qinkun Bao via llvm-branch-commits
https://github.com/qinkunbao closed https://github.com/llvm/llvm-project/pull/140821 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang] callee_type metadata for indirect calls (PR #117036)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const NamedDecl *ND) { GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage); } +static bool hasExistingGeneralizedTypeMD(llvm::Function *F) { + llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext

[llvm-branch-commits] [clang] [clang] callee_type metadata for indirect calls (PR #117036)

2025-05-22 Thread Paul Kirth via llvm-branch-commits
@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const NamedDecl *ND) { GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage); } +static bool hasExistingGeneralizedTypeMD(llvm::Function *F) { + llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext

[llvm-branch-commits] [llvm] [HLSL][RootSignature] Implement serialization of `RootConstants` and `RootFlags` (PR #141130)

2025-05-22 Thread via llvm-branch-commits
llvmbot wrote: @llvm/pr-subscribers-hlsl Author: Finn Plummer (inbelic) Changes - Implements serialization of the currently completely defined `RootElement`s, namely `RootConstants` and `RootFlags` - Adds unit testing for the serialization methods Resolves: https://github.com/llvm/llvm-p

[llvm-branch-commits] [llvm] [HLSL][RootSignature] Implement serialization of `RootConstants` and `RootFlags` (PR #141130)

2025-05-22 Thread Finn Plummer via llvm-branch-commits
https://github.com/inbelic created https://github.com/llvm/llvm-project/pull/141130 - Implements serialization of the currently completely defined `RootElement`s, namely `RootConstants` and `RootFlags` - Adds unit testing for the serialization methods Resolves: https://github.com/llvm/llvm-pro

[llvm-branch-commits] [llvm] AMDGPU: Form v_med_f32 from minimumnum/maximumnum immediate pattern (PR #141048)

2025-05-22 Thread Matt Arsenault via llvm-branch-commits
arsenm wrote: ### Merge activity * **May 22, 6:57 PM UTC**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/141048). https://github.com/llvm/llvm-project/pull/141048 _

[llvm-branch-commits] [llvm] [NFCI] Avoid adding duplicated SpecialCaseList::Sections. (PR #140821)

2025-05-22 Thread Qinkun Bao via llvm-branch-commits
qinkunbao wrote: > Make Glob a vector added in parsing order Yeah, that is needed. > Make sections a vector added in parsing order It is not necessary. > duplicate entries is not a problem as they should not be common It is not common but we need to iterate all the sections every time to ensu

[llvm-branch-commits] [llvm] AMDGPU: Form v_med_f32 from minimumnum/maximumnum immediate pattern (PR #141048)

2025-05-22 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141048 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)

2025-05-22 Thread Matt Arsenault via llvm-branch-commits
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/132385 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NFC] Refactoring DXContainerYaml Root Parameter representation (PR #138318)

2025-05-22 Thread via llvm-branch-commits
https://github.com/joaosaffran converted_to_draft https://github.com/llvm/llvm-project/pull/138318 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NFCI] Avoid adding duplicated SpecialCaseList::Sections. (PR #140821)

2025-05-22 Thread Vitaly Buka via llvm-branch-commits
vitalybuka wrote: > Hi Vitaly, > > Sorry for the late reply. I am thinking about a good solution for #139772 in > the past two days. > > At the moment, I am thinking only the order of `Globs` and `RegExes` (Or > `Pattern`) matters. The order of `Section`, `Prefix` and `Category` does not > m

[llvm-branch-commits] [llvm] [NFCI] Avoid adding duplicated SpecialCaseList::Sections. (PR #140821)

2025-05-22 Thread Qinkun Bao via llvm-branch-commits
qinkunbao wrote: Hi Vitaly, Sorry for the late reply. I am thinking about a good solution for https://github.com/llvm/llvm-project/pull/139772 in the past two days. At the moment, I am thinking only the order of `Globs` and `RegExes` (Or `Pattern`) matters. The order of `Section`, `Prefix` a

[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add parsing of flags to RootDescriptor (PR #140152)

2025-05-22 Thread Alex Sepkowski via llvm-branch-commits
alsepkow wrote: Reviewed but don't have approval permissions yet. LGTM! https://github.com/llvm/llvm-project/pull/140152 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [clang] [llvm] [HLSL][RootSignature] Add parsing of optional parameters for RootDescriptor (PR #140151)

2025-05-22 Thread Alex Sepkowski via llvm-branch-commits
alsepkow wrote: Reviewed but don't have approval permissions yet. LGTM! https://github.com/llvm/llvm-project/pull/140151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [libclc] release/20.x: [libclc] Include isnan implementation for SPIR-V targets (PR #140902)

2025-05-22 Thread Karol Herbst via llvm-branch-commits
https://github.com/karolherbst updated https://github.com/llvm/llvm-project/pull/140902 >From 19163b472984a6c3f8df599d95763794c8d9e3ec Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Wed, 21 May 2025 15:57:38 +0200 Subject: [PATCH] [libclc] Include isnan implementation for SPIR-V targets The

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Matt Arsenault via llvm-branch-commits
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/132383 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Matt Arsenault via llvm-branch-commits
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI, case Ext32To64: { const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); MachineInstrBuilder Hi; - -if (MI.getOpcode() == AMDGPU::G_ZEXT) { +switch (MI.getOpcode()) { +c

[llvm-branch-commits] [clang] [KeyInstr] Complex assignment atoms (PR #134638)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -1356,6 +1361,7 @@ LValue ComplexExprEmitter::EmitBinAssignLValue(const BinaryOperator *E, } ComplexPairTy ComplexExprEmitter::VisitBinAssign(const BinaryOperator *E) { + ApplyAtomGroup Grp(CGF.getDebugInfo()); ComplexPairTy Val; LValue LV = EmitBinAssignLValue(E, V

[llvm-branch-commits] [clang] [KeyInstr] Complex assignment atoms (PR #134638)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -1209,6 +1213,7 @@ LValue ComplexExprEmitter:: EmitCompoundAssignLValue(const CompoundAssignOperator *E, ComplexPairTy (ComplexExprEmitter::*Func)(const BinOpInfo&), RValue &Val) { + ApplyAtomGroup Grp(CGF.getDebugInfo());

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (PR #132382)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/132382 >From c08c9f0916b724d733ea47e944137e0a8952d365 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Thu, 8 May 2025 12:02:27 +0200 Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/132383 >From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Thu, 8 May 2025 12:03:28 +0200 Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/132385 >From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Mon, 14 Apr 2025 16:35:19 +0200 Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s

[llvm-branch-commits] [mlir] Add missing imports (PR #138550)

2025-05-22 Thread Nikita Popov via llvm-branch-commits
nikic wrote: The LLVM 19 release is no longer supported. You'll have to apply this as a local patch if you want to build and old LLVM 19 with a new libstdc++. https://github.com/llvm/llvm-project/pull/138550 ___ llvm-branch-commits mailing list llvm-b

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/132383 >From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Thu, 8 May 2025 12:03:28 +0200 Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/132385 >From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Mon, 14 Apr 2025 16:35:19 +0200 Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s

[llvm-branch-commits] [mlir] Add missing imports (PR #138550)

2025-05-22 Thread Nikita Popov via llvm-branch-commits
https://github.com/nikic closed https://github.com/llvm/llvm-project/pull/138550 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Jeremy Morse via llvm-branch-commits
https://github.com/jmorse approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/134637 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
OCHyams wrote: Thanks @jmorse, that should be all nits/questions addressed now. https://github.com/llvm/llvm-project/pull/134637 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llv

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
https://github.com/OCHyams updated https://github.com/llvm/llvm-project/pull/134637 >From 3b4ca1b09a659e575e022109fd8c607c9df3864f Mon Sep 17 00:00:00 2001 From: Orlando Cazalet-Hyams Date: Wed, 2 Apr 2025 18:01:48 +0100 Subject: [PATCH 01/12] [KeyInstr][Clang] Assignment atom group This patch

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -5849,6 +5852,7 @@ LValue CodeGenFunction::EmitObjCIsaExpr(const ObjCIsaExpr *E) { LValue CodeGenFunction::EmitCompoundAssignmentLValue( const CompoundAssignOperator *E) { + ApplyAtomGroup Grp(getDebugInfo()); O

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -0,0 +1,41 @@ + +// RUN: %clang -gkey-instructions -x c++ %s -gmlt -gno-column-info -S -emit-llvm -o - -ftrivial-auto-var-init=pattern \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang -gkey-instructions -x c %s -gmlt -gn

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const BinaryOperator *E) { OCHyams wrote: Yeah that's right - added to the test for better coverage. https://github.com/llvm/llvm-project/pull/134637 _

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang_cc1 -gkey-instructions -x c %s -debug-info-kind=line-tabl

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -0,0 +1,41 @@ + +// RUN: %clang -gkey-instructions -x c++ %s -gmlt -gno-column-info -S -emit-llvm -o - -ftrivial-auto-var-init=pattern \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank + +// RUN: %clang -gkey-instructions -x c %s -gmlt -gn

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -0,0 +1,48 @@ +// RUN: %clang_cc1 -gkey-instructions -x c++ %s -debug-info-kind=line-tables-only -emit-llvm -o - \ +// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not atomRank OCHyams wrote: Done https://github.com/llvm/llvm-project/

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
https://github.com/OCHyams updated https://github.com/llvm/llvm-project/pull/134637 >From 3b4ca1b09a659e575e022109fd8c607c9df3864f Mon Sep 17 00:00:00 2001 From: Orlando Cazalet-Hyams Date: Wed, 2 Apr 2025 18:01:48 +0100 Subject: [PATCH 01/11] [KeyInstr][Clang] Assignment atom group This patch

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const BinaryOperator *E) { assert(E->getOpcode() == BO_Assign && "unexpected binary l-value"); + // This covers both LHS and RHS expressions, though nested RHS + // expressions may get subsequently s

[llvm-branch-commits] [clang] [KeyInstr][Clang] Assignment atom group (PR #134637)

2025-05-22 Thread Orlando Cazalet-Hyams via llvm-branch-commits
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const BinaryOperator *E) { assert(E->getOpcode() == BO_Assign && "unexpected binary l-value"); + // This covers both LHS and RHS expressions, though nested RHS + // expressions may get subsequently s

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
@@ -70,14 +70,29 @@ define i8 @v_ashr_i8_7(i8 %value) { } define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) { -; GCN-LABEL: s_ashr_i8: -; GCN: ; %bb.0: -; GCN-NEXT:s_sext_i32_i8 s0, s0 -; GCN-NEXT:s_ashr_i32 s0, s0, s1 -; GCN-NEXT:; return to

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy, MI.eraseFromParent(); } +void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) { + Register Dst = MI.getOperand(0).getReg(); + LLT Ty = MRI.getType(Dst); + Register Src = MI

[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: clarify MCPlusBuilder callbacks interface (PR #136147)

2025-05-22 Thread Kristof Beyls via llvm-branch-commits
@@ -985,6 +985,26 @@ inst_pacnbibsppc: ret .size inst_pacnbibsppc, .-inst_pacnbibsppc +// Test that write-back forms of LDRA(A|B) instructions are handled properly. + +.globl inst_ldraa_wb +.type inst_ldraa_wb,@function +inst_ldraa_wb: +// CH

[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)

2025-05-22 Thread Petar Avramovic via llvm-branch-commits
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI, case Ext32To64: { const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); MachineInstrBuilder Hi; - -if (MI.getOpcode() == AMDGPU::G_ZEXT) { +switch (MI.getOpcode()) { +c

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