https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/132540
>From de28401e6c4f68117f0b71f2b08c3c065b286f62 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 20 Mar 2025 20:15:07 +0300
Subject: [PATCH] [BOLT] Gadget scanner: Detect address materialization a
github-actions[bot] wrote:
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@@ -54,12 +54,11 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public
Generic_ELF {
return UnwindTableLevel::None;
}
- RuntimeLibType GetDefaultRuntimeLibType() const override {
-return ToolChain::RLT_CompilerRT;
- }
- CXXStdlibType GetDefaultCXXStdlibType() const
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain
@@ -534,8 +554,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("-Bstatic");
- if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+ if (Triple.isRISCV()) {
+if (A
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
petr
@@ -18,6 +18,6 @@
.globl _start
_start:
.data
- .word foo@PLT - .
- .word foo@PLT - . + 1
- .word foo@PLT - . - 1
+ .word %plt(foo - .)
jrtc27 wrote:
I've not looked at the implementation in detail, but thank you for taking the
time to do so, I know from
https://github.com/zyn0217 approved this pull request.
Sorry for missing this. LGTM assuming @hokein is happy too.
https://github.com/llvm/llvm-project/pull/131074
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https://github.com/llvm/llvm-project/pull/130950
>From ecde8c235e5e09ff71789725c96416f8daf93cd7 Mon Sep 17 00:00:00 2001
From: Matheus Izvekov
Date: Sat, 8 Mar 2025 20:32:14 -0300
Subject: [PATCH] [clang] fix matching of nested template template parameters
W
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/132806
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@@ -18,6 +18,6 @@
.globl _start
_start:
.data
- .word foo@PLT - .
- .word foo@PLT - . + 1
- .word foo@PLT - . - 1
+ .word %plt(foo - .)
MaskRay wrote:
Implemented `%pltpcrel`, while a bit complex, I am happy with the result. (As
in `RISCVMCExpr::evaluateA
quic-garvgupt wrote:
Hi @petrhosek @MaskRay, can you review this PR as well. This PR is also the
part of the ongoing series of patches for merging RISCVToolchain object into
baremetal toolchain object
https://github.com/llvm/llvm-project/pull/121831
@@ -0,0 +1,164 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030
-run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
cdevadas wrote:
Drop the -verify-
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030
-run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
cdevadas wrote:
Ditto.
https://gi
https://github.com/SixWeining approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/133027
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@@ -1375,14 +1375,20 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr
expr, RelType type,
return 1;
}
+ // LoongArch support IE to LE optimization in non-extreme code model.
+ bool execOptimizeInLoongArch =
+ ctx.arg.emachine == EM_LOONGARCH &&
+ (
MaskRay wrote:
LGTM.
Note: test/CodeGen is probably not the best place for such tests.
`test/MC/CSKY/relocation-specifier.s` contains a nice example and tests
multiple relocations at the same time.
https://github.com/llvm/llvm-project/pull/133027
__
https://github.com/david-xl approved this pull request.
https://github.com/llvm/llvm-project/pull/129781
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https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cp
@@ -0,0 +1,131 @@
+target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-grtev4-linux-gnu"
+
+; Tests that constant pool hotness is aggregated across the module. The
snehasish wrote:
I thin
https://github.com/snehasish edited
https://github.com/llvm/llvm-project/pull/129781
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Author: Matheus Izvekov
Date: 2025-03-25T16:56:10-07:00
New Revision: ecde8c235e5e09ff71789725c96416f8daf93cd7
URL:
https://github.com/llvm/llvm-project/commit/ecde8c235e5e09ff71789725c96416f8daf93cd7
DIFF:
https://github.com/llvm/llvm-project/commit/ecde8c235e5e09ff71789725c96416f8daf93cd7.dif
https://github.com/tstellar closed
https://github.com/llvm/llvm-project/pull/130950
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https://github.com/llvm/llvm-project/pull/129997
>From fcd0ad23f668bce4b3a3731c5baa115434dc3269 Mon Sep 17 00:00:00 2001
From: David Green
Date: Tue, 4 Mar 2025 21:46:55 +
Subject: [PATCH 1/2] [AArch64] Add test for scalar copysign. NFC
(cherry picked fro
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Author: David Green
Date: 2025-03-25T15:52:21-07:00
New Revision: dc7b743515d3a463465dd38a62869ab9f77704cd
URL:
https://github.com/llvm/llvm-project/commit/dc7b743515d3a463465dd38a62869ab9f77704cd
DIFF:
https://github.com/llvm/llvm-project/commit/dc7b743515d3a463465dd38a62869ab9f77704cd.diff
L
Author: David Green
Date: 2025-03-25T15:52:20-07:00
New Revision: fcd0ad23f668bce4b3a3731c5baa115434dc3269
URL:
https://github.com/llvm/llvm-project/commit/fcd0ad23f668bce4b3a3731c5baa115434dc3269
DIFF:
https://github.com/llvm/llvm-project/commit/fcd0ad23f668bce4b3a3731c5baa115434dc3269.diff
L
llvmbot wrote:
@RKSimon What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/132932
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llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: None (llvmbot)
Changes
Backport 481a55a3d9645a6bc1540d326319b78ad8ed8db1
Requested by: @wrotki
---
Full diff: https://github.com/llvm/llvm-project/pull/132997.diff
2 Files Affected:
- (modified) compiler-rt/lib/rtsan/rt
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/133006
Backport ab58a3c35b6fc6a4b513d75c38881134f5b2c9b9
Requested by: @wrotki
>From 50c746f024a9d6ddbbef2a2a89f6cd62540e9435 Mon Sep 17 00:00:00 2001
From: Mariusz Borsa
Date: Thu, 13 Mar 2025 16:01:32 -0700
Subject
https://github.com/llvmbot milestoned
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@@ -355,12 +355,12 @@ class CGDebugInfo {
llvm::ArrayRef PreviousFieldsDI, const RecordDecl *RD);
/// A cache that maps names of artificial inlined functions to subprograms.
- llvm::StringMap InlinedTrapFuncMap;
+ llvm::StringMap InlinedSubprogramMap;
---
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cp
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cp
@@ -3598,6 +3598,14 @@ llvm::DIMacroFile
*CGDebugInfo::CreateTempMacroFile(llvm::DIMacroFile *Parent,
return DBuilder.createTempMacroFile(Parent, Line, FName);
}
+llvm::DILocation *CGDebugInfo::CreateSyntheticInline(llvm::DebugLoc Location,
+
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/128977
>From 0fe2ba3242026457d8afc46c4a3338efd941c42f Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Wed, 26 Feb 2025 17:12:43 -0800
Subject: [PATCH 1/4] fmt
Created using spr 1.3.4
---
clang/lib/CodeGen/CGExpr.cp
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: None (llvmbot)
Changes
Backport ab58a3c35b6fc6a4b513d75c38881134f5b2c9b9
Requested by: @wrotki
---
Full diff: https://github.com/llvm/llvm-project/pull/133006.diff
1 Files Affected:
- (modified) compiler-rt/test/sanitiz
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/118878
>From 1447ec21597f752b29e367a46f06eecdf9c81dd7 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Wed, 30 Oct 2024 13:34:21 -0500
Subject: [PATCH 1/2] [clang][OpenMP] Add AST node for root of compound
di
wrotki wrote:
@cjappl I misunderstood @thetruestblue 's request, she asked me to cherry-pick
XFAIL on the test, not your change. Apologies - I'll let you cherry-pick this
yourself once you decide it's ready 🙂
https://github.com/llvm/llvm-project/pull/132997
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Author: Emilio Cota
Date: 2025-03-25T21:35:52Z
New Revision: 9c438311e573094c76c2b2d2425d625e068f841a
URL:
https://github.com/llvm/llvm-project/commit/9c438311e573094c76c2b2d2425d625e068f841a
DIFF:
https://github.com/llvm/llvm-project/commit/9c438311e573094c76c2b2d2425d625e068f841a.diff
LOG: R
llvmbot wrote:
@cjappl What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/132997
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@@ -577,6 +577,16 @@ class MCPlusBuilder {
return getNoRegister();
}
+ /// Returns the register used as call destination, or no-register, if not
+ /// an indirect call. Sets IsAuthenticatedInternally if the instruction
+ /// accepts signed pointer as its operand and a
https://github.com/petrhosek approved this pull request.
https://github.com/llvm/llvm-project/pull/132808
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https://github.com/snehasish approved this pull request.
lgtm with some suggested changes to the tests.
https://github.com/llvm/llvm-project/pull/129781
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@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Repeat the RUN com
@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Repeat the RUN com
@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
+; RUN: -partition-static-data-sections=true -function-sections=true \
+; RUN: -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --dump-input=always
+
+; Repeat the RUN com
@@ -0,0 +1,141 @@
+; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \
snehasish wrote:
Can we drop the `-enable-split-machine-functions` flag here and below?
https://github.com/llvm/llvm-project/pull/129781
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release:note label to this PR.
Author: Martin Storsjö
Date: 2025-03-25T13:15:01-07:00
New Revision: 66825a89b8e0e9e1d202cb4d3824791b81afdc98
URL:
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DIFF:
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>From 66825a89b8e0e9e1d202cb4d3824791b81afdc98 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=C3=B6?=
Date: Fri, 21 Mar 2025 15:33:25 +0200
Subject: [PATCH] [LLD] [COFF] Add a few more mingw libs to sk
github-actions[bot] wrote:
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https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/132540
>From de28401e6c4f68117f0b71f2b08c3c065b286f62 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 20 Mar 2025 20:15:07 +0300
Subject: [PATCH] [BOLT] Gadget scanner: Detect address materialization a
alexrp wrote:
Seems like the tests are failing because #126880 hasn't been backported.
Probably should just adjust the tests accordingly.
What's standard practice here? Should someone with commit access just push a
fix to the PR branch?
https://github.com/llvm/llvm-project/pull/132049
___
yxsamliu wrote:
> > Clang adds !amdgpu.no.fine.grained.memory and !amdgpu.no.remote.memory to
> > any atomic instructions by default. I think this behavior is expected to
> > keep ISA unchanged compared to the ISA before these metatadat were
> > introduced. Did I miss anything?
>
> All of the
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: None (llvmbot)
Changes
Backport 975c208556ef85b321a223fe592fa6d98fadfaa0
Requested by: @phoebewang
---
Patch is 106.53 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/132932.diff
15 Files Affect
https://github.com/aeubanks approved this pull request.
https://github.com/llvm/llvm-project/pull/132864
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@@ -577,6 +577,16 @@ class MCPlusBuilder {
return getNoRegister();
}
+ /// Returns the register used as call destination, or no-register, if not
+ /// an indirect call. Sets IsAuthenticatedInternally if the instruction
+ /// accepts signed pointer as its operand and a
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/130967
>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/3] Add missing NO-VIS lines
Created using spr 1.3.5
---
llvm/test/M
https://github.com/koachan updated
https://github.com/llvm/llvm-project/pull/130967
>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/3] Add missing NO-VIS lines
Created using spr 1.3.5
---
llvm/test/M
https://github.com/cor3ntin approved this pull request.
https://github.com/llvm/llvm-project/pull/132697
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@@ -0,0 +1,676 @@
+// RUN: %clang %cflags -march=armv8.3-a %s -o %t.exe
+// RUN: llvm-bolt-binary-analysis --scanners=pacret %t.exe 2>&1 | FileCheck %s
kbeyls wrote:
I'm wondering if the user interface for this should be adapted?
`pac-ret` is a widely deployed h
https://github.com/kbeyls edited
https://github.com/llvm/llvm-project/pull/131899
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https://github.com/kbeyls commented:
I haven't had time yet to review the test cases, but I thought I'd share my
comments so far already.
https://github.com/llvm/llvm-project/pull/131899
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@@ -0,0 +1,676 @@
+// RUN: %clang %cflags -march=armv8.3-a %s -o %t.exe
+// RUN: llvm-bolt-binary-analysis --scanners=pacret %t.exe 2>&1 | FileCheck %s
+
+// FIXME In the below test cases, LR is usually not spilled as needed, as it is
+// not checked by BOLT.
---
@@ -382,11 +382,11 @@ class PacRetAnalysis
public:
std::vector
- getLastClobberingInsts(const MCInst Ret, BinaryFunction &BF,
- const ArrayRef UsedDirtyRegs) const {
kbeyls wrote:
I was wondering whether `const` has to be removed he
@@ -277,6 +277,48 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ MCPhysReg
+ getRegUsedAsCallDest(const MCInst &Inst,
+ bool &IsAuthenticatedInternally) const override {
kbeyls wrote:
I'm wondering if this could be
https://github.com/RKSimon approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/132932
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 077eae0ad90d07540f3d84ac084488bc29cbf37e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 04:58:57 -0700
Subject: [PATCH] [Driver] Add support for crtbegin.o, crtend.o and libgloss
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 9985dc44013cce96c62847c91a6a07f56b295094 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From 7aef889e3fbd5140a484a1f0d56832cd7bd192a7 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
@@ -16,7 +16,7 @@
// C-AARCH64-BAREMETAL: "-cc1" "-triple" "aarch64-unknown-none-elf"
// C-AARCH64-BAREMETAL: "-isysroot"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf"
// C-AARCH64-BAREMETAL: "-internal-isystem"
"{{.*}}Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/i
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 5efd1f2166deb15c7a8de505c7851954d7e31c71 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From 6480848c32fad1fc9f69ff1d445bbb7932afd428 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132807
>From 22c7d24f4e27a907306bef8f946946ff80c1d48f Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:49:09 -0700
Subject: [PATCH] [Driver] Add option to force udnefined symbols during linki
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132806
>From 66c86ddfd852b3f70aa5fde9002ef0d6e5735274 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:17:42 -0700
Subject: [PATCH] [Driver] Fix link order of BareMetal toolchain object
The
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/132806
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matthias-springer wrote:
> I think this is OK, but when we create a new memref, dont we want to verify
> that the strides specified dont make it such that accessing using strides
> goes out of bounds?
By "create a new memref" you mean the reinterpret_cast result, right? I'd say
you don't want
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