https://github.com/HerrCai0907 updated
https://github.com/llvm/llvm-project/pull/130417
>From 1706e3fc5819602febf9dfa554e98eb1e1fea365 Mon Sep 17 00:00:00 2001
From: Congcong Cai
Date: Sat, 8 Mar 2025 21:50:19 +0800
Subject: [PATCH] [clang-tidy] support to detect conversion in `make_optional`
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129853
>From 19662079ef1d5ede80dc6cdf0d8c0983033b15ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 08:59:23 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port MachineBlockPlacementStats to NPM
---
..
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129853
>From 957ca954e2bdaf7f1c3dc841eeeadf76e2580ce8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 08:59:23 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port MachineBlockPlacementStats to NPM
---
..
https://github.com/PiotrZSL requested changes to this pull request.
You may need to update documentation for this matcher in
clang/docs/LibASTMatchersReference.html
https://github.com/llvm/llvm-project/pull/130416
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@@ -497,3 +497,49 @@ signature and passed to the shader without requiring a
constant buffer resource:
#. **Num32BitValues**: The number of 32-bit values included in this constant
buffer.
Root constants provide a fast way to pass small amounts of data directly to
the shader
@@ -0,0 +1,45 @@
+! Tests that if `do concurrent` is not perfectly nested in its parent loop,
that
+! we skip converting the not-perfectly nested `do concurrent` loop.
+
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=host %s -o - \
+! RUN: | FileCheck %s
+
+p
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/127633
>From 2e6bf4c394db115bd4a369473742b7411a03334c Mon Sep 17 00:00:00 2001
From: ergawy
Date: Tue, 18 Feb 2025 02:50:46 -0600
Subject: [PATCH 1/3] [flang][OpenMP] Map simple `do concurrent` loops to
OpenMP host con
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/130323
>From 80765757f067527816c4c8b9d728169568b04b7a Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Fri, 7 Mar 2025 10:40:20 -0800
Subject: [PATCH 1/2] [DirectX] Remove DXILResourceMDAnalysis
Part 1/2 of #114126
--
MaskRay wrote:
> We're facing it again, with LLVM20 this time
... which indicates that the distro and boost should really fix the problem and
not rely on the clang driver hacks.
https://github.com/llvm/llvm-project/pull/102039
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@llvm/pr-subscribers-clang-format
Author: None (llvmbot)
Changes
Backport 7d4d8509cbec7eecd8aaf2510015b54bc5c173e1
Requested by: @owenca
---
Full diff: https://github.com/llvm/llvm-project/pull/130702.diff
2 Files Affected:
- (modified) clang/lib/Format/UnwrappedLinePar
llvmbot wrote:
@HazardyKnusperkeks What do you think about merging this PR to the release
branch?
https://github.com/llvm/llvm-project/pull/130702
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https://github.com/frederick-vs-ja approved this pull request.
https://github.com/llvm/llvm-project/pull/130658
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https://github.com/bogner approved this pull request.
https://github.com/llvm/llvm-project/pull/130342
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@@ -99,18 +96,6 @@ static NamedMDNode *emitResourceMetadata(Module &M,
DXILBindingMap &DBM,
Metadata *SmpMD = Smps.empty() ? nullptr : MDNode::get(Context, Smps);
bool HasResources = !DBM.empty();
- if (MDResources.hasUAVs()) {
-assert(!UAVMD && "Old and new UAV repr
https://github.com/ritter-x2a created
https://github.com/llvm/llvm-project/pull/130617
If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the new GEPs are inbounds.
For SWDEV-516125.
>From e88
@@ -2769,6 +2769,23 @@ namespace {
} // end anonymous namespace
+StringRef AsmPrinter::getConstantSectionSuffix(const Constant *C) const {
snehasish wrote:
Consider refactoring a bit to reduce nesting --
```
if(!TM.Options.EnableStaticDataPartitioning || C
@@ -2769,6 +2769,23 @@ namespace {
} // end anonymous namespace
+StringRef AsmPrinter::getConstantSectionSuffix(const Constant *C) const {
+ SmallString<8> SectionNameSuffix;
+ if (TM.Options.EnableStaticDataPartitioning) {
+if (C && SDPI && PSI) {
+ auto Count = S
pawosm-arm wrote:
We're facing it again, with LLVM20 this time
https://github.com/llvm/llvm-project/pull/102039
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@@ -66,21 +69,44 @@ class RemoveLoadsIntoFakeUses : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
};
-char RemoveLoadsIntoFakeUses::ID = 0;
-char &llvm::RemoveLoadsIntoFakeUsesID = RemoveLoadsIntoFakeUses::ID;
+struct RemoveLoadsIntoFa
@@ -88,6 +89,45 @@ struct PerfSpeEventsTestHelper : public testing::Test {
return SampleSize == DA.BasicSamples.size();
}
+
+ /// Compare LBREntries
+ bool checkLBREntry(const LBREntry &Lhs, const LBREntry &Rhs) {
+return Lhs.From == Rhs.From && Lhs.To == Rhs.To &&
https://github.com/paschalis-mpeis edited
https://github.com/llvm/llvm-project/pull/129231
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@@ -497,3 +497,49 @@ signature and passed to the shader without requiring a
constant buffer resource:
#. **Num32BitValues**: The number of 32-bit values included in this constant
buffer.
Root constants provide a fast way to pass small amounts of data directly to
the shader
@@ -11,4 +11,4 @@ CHECK-SPE-NO-LBR: PERF2BOLT: Starting data aggregation job
RUN: perf record -e cycles -q -o %t.perf.data -- %t.exe
RUN: not perf2bolt -p %t.perf.data -o %t.perf.boltdata --spe %t.exe 2>&1 |
FileCheck %s --check-prefix=CHECK-SPE-LBR
-CHECK-SPE-LBR: PERF2BOLT-
@@ -1034,7 +1034,11 @@ ErrorOr DataAggregator::parseLBREntry() {
if (std::error_code EC = MispredStrRes.getError())
return EC;
StringRef MispredStr = MispredStrRes.get();
- if (MispredStr.size() != 1 ||
+ // SPE brstack mispredicted flags might be two characters long:
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130060
>From b1402edb380ddf044af4810a9b7a88c4f874c0ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 11:06:40 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIMemoryLegalizer to NPM
---
llvm/lib/Tar
@@ -742,6 +730,36 @@ class SIInsertWaitcnts : public MachineFunctionPass {
WaitcntBrackets &ScoreBrackets);
};
+class SIInsertWaitcntsLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ SIInsertWaitcntsLegacy() : MachineFunctionPass
@@ -40,30 +41,45 @@ using namespace llvm;
STATISTIC(NumNoops, "Number of noops inserted");
namespace {
- class PostRAHazardRecognizer : public MachineFunctionPass {
+struct PostRAHazardRecognizer {
+ bool run(MachineFunction &MF);
+};
- public:
-static char ID;
-P
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff c29d8202c06488a9466aea49dda4cf2b4663236e
296a9db2611c31497fb40b5b01a027440dcda2a5 --e
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/4] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/5] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/3] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130094
>From aff1e132263dba730999eb017b7548a5d2f46b6f Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 10 Oct 2023 11:06:23 +0200
Subject: [PATCH 1/2] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain
The llvm
@@ -276,16 +288,49 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU)
const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130069
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https://github.com/llvm/llvm-project/pull/130068
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@@ -152,26 +199,140 @@ class DoConcurrentConversion : public
mlir::OpConversionPattern {
public:
using mlir::OpConversionPattern::OpConversionPattern;
- DoConcurrentConversion(mlir::MLIRContext *context, bool mapToDevice)
- : OpConversionPattern(context), mapToDevice(
@@ -24,7 +25,50 @@ namespace flangomp {
namespace {
namespace looputils {
-using LoopNest = llvm::SetVector;
+/// Stores info needed about the induction/iteration variable for each `do
+/// concurrent` in a loop nest.
+struct InductionVariableInfo {
+ /// the operation alloca
@@ -0,0 +1,45 @@
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=host %s -o - \
+! RUN: | FileCheck %s
+
+program main
+implicit none
+
+call foo(10)
+
+contains
+subroutine foo(n)
+implicit none
+integer :: n
+
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130067
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@@ -744,7 +753,15 @@ bool BranchRelaxation::relaxBranchInstructions() {
return Changed;
}
-bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
+PreservedAnalyses
+BranchRelaxationPass::run(MachineFunction &MF,
+ MachineFunctionAnalysis
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs
-run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -
@@ -1,6 +1,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass
post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs
-run-pass post-RA-hazard-rec %s -o - | FileC
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-pre-emit-peephole
-verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=si-pre-emit-peep
@@ -96,12 +108,20 @@ static bool isVMEMLoad(const MachineInstr &MI) {
return SIInstrInfo::isVMEM(MI) && MI.mayLoad();
}
-bool AMDGPUSetWavePriority::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+llvm::AMDGPUSetWavePriorityPass::run(MachineFunction &MF,
+
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130064
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@@ -2,6 +2,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64
-run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck
-check-prefixes=GCN,GFX10 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64
-run-pass=si-late-branch
@@ -1,4 +1,5 @@
# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji
-run-pass=si-late-branch-lowering -verify-machineinstrs | FileCheck
-check-prefix=GCN %s
+# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -passes=si-late-branch-lowering
-verify-machineinstrs | FileCheck -check-prefix
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass
si-insert-hard-clauses %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130060
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No tests for this pass?
https://github.com/llvm/llvm-project/pull/129857
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llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: None (llvmbot)
Changes
Backport dd21aacd76e36d4db157a5d7a7b5370d456426e6
Requested by: @DianQK
---
Full diff: https://github.com/llvm/llvm-project/pull/130585.diff
3 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineI
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/130585
Backport dd21aacd76e36d4db157a5d7a7b5370d456426e6
Requested by: @DianQK
>From 5449b176ebe63b354ac63e177aff9215c4726060 Mon Sep 17 00:00:00 2001
From: DianQK
Date: Mon, 10 Mar 2025 19:34:07 +0800
Subject: [PATC
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: None (llvmbot)
Changes
Backport 8d38906d08f0189a7a7f865b267f47cab0a3790f
Requested by: @marcauberer
---
Full diff: https://github.com/llvm/llvm-project/pull/130580.diff
1 Files Affected:
- (modified) llvm/lib/IR/User.cpp (+6)
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Backport 8d38906d08f0189a7a7f865b267f47cab0a3790f
Requested by: @marcauberer
>From b3515aa07b42164268a835e3f5874f49056a2e22 Mon Sep 17 00:00:00 2001
From: Marc Auberer
Date: Mon, 10 Mar 2025 11:53:45 +0100
Sub
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/128520
>From 652675b203aebda23fcccdd1b411c2aa51181e15 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 17 Nov 2023 14:21:52 +0900
Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue
blo
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/128520
>From 652675b203aebda23fcccdd1b411c2aa51181e15 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 17 Nov 2023 14:21:52 +0900
Subject: [PATCH] AMDGPU: Implement bitcode autoupgrade for old style enqueue
blo
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Akshat Oke (optimisan)
Changes
Not sure why this is squished into VirtRegMap.h
---
Full diff: https://github.com/llvm/llvm-project/pull/130564.diff
12 Files Affected:
- (modified) llvm/include/llvm/CodeGen/VirtRegMap.h (+15)
- (m
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
Not sure why this is squished into VirtRegMap.h
---
Full diff: https://github.com/llvm/llvm-project/pull/130564.diff
12 Files Affected:
- (modified) llvm/include/llvm/CodeGen/VirtRegMap.h (+15)
-
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/130564
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https://github.com/llvm/llvm-project/pull/130564
>From 0f09f5616d4b681df5349333991748070e07182c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 10 Mar 2025 06:14:27 +
Subject: [PATCH] [CodeGen][NPM] Port VirtRegRewriter to NPM
Not sure why this is
github-actions[bot] wrote:
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:warning:
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git-clang-format --diff f20b44edd8de0001efd809147599e48966e51606
061150df047480e1bcf44460b0ff745e5d6a4b65 --e
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/130060
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mariusz-sikora-at-amd wrote:
ping
https://github.com/llvm/llvm-project/pull/130041
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@@ -1200,34 +1225,78 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB,
MachineInstr &MI,
MDT->applyUpdates(DTUpdates);
}
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+ if (Op.isReg
@@ -172,7 +215,12 @@ bool
SILateBranchLowering::runOnMachineFunction(MachineFunction &MF) {
case AMDGPU::SI_CS_CHAIN_TC_W32:
case AMDGPU::SI_CS_CHAIN_TC_W64:
-expandChainCall(MI);
+expandChainCall(MI, ST, /*DynamicVGPR*/ false);
+MadeChange
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