kartcq wrote:
[like] Karthika Devi C reacted to your message:
From: Eli Friedman ***@***.***>
Sent: Monday, February 3, 2025 1:40:45 AM
To: llvm/llvm-project ***@***.***>
Cc: Karthika Devi C (QUIC) ***@***.***>; Review requested ***@***.***>
Subject: Re: [llvm/ll
@@ -1842,19 +1842,19 @@ class ClassTemplateSpecializationDecl : public
CXXRecordDecl,
unsigned SpecializationKind : 3;
/// Indicate that we have matched a parameter pack with a non pack
- /// argument, when the opposite match is also allowed (strict pack match).
+ /// a
https://github.com/aemerson approved this pull request.
https://github.com/llvm/llvm-project/pull/125386
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https://github.com/MaskRay approved this pull request.
https://github.com/llvm/llvm-project/pull/125334
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/125432
>From 1c10a4c81c1c8d05ed62ab5fa1ee24539f76f889 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 31 Jan 2025 13:12:56 -0500
Subject: [PATCH] [SelectionDAG][X86] Remove unused elements from atomic
vector.
After spl
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From d1a877b226e5e72b5131f26db78491553c774bb0 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From d1a877b226e5e72b5131f26db78491553c774bb0 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From d1a877b226e5e72b5131f26db78491553c774bb0 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn edited https://github.com/llvm/llvm-project/pull/120640
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 76e068350de93eee06b3cc4616adadf33e9d84c0
fbe99a2a2d6f3c95978c520812046567ec7811cd --e
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Backport 9052b37ab1aa67a039b34356f37236fecc42bac2
Requested by: @mgorny
>From 03d6f704d07aa3650a2f59be6f7802a8735460c3 Mon Sep 17 00:00:00 2001
From: Lang Hames
Date: Wed, 29 Jan 2025 03:58:29 +
Subject: [
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 05e7afdcb910b7773f65159b3ee431b39527b4c1 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From 76e068350de93eee06b3cc4616adadf33e9d84c0 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn edited https://github.com/llvm/llvm-project/pull/120385
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llvmbot wrote:
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-backend-x86
Author: None (jofrn)
Changes
After splitting, all elements are created. The elements are
placed back into a concat_vectors. This change extends EltsFromConsecutiveLoads
to understand AtomicSDNode so that
https://github.com/jofrn edited https://github.com/llvm/llvm-project/pull/120640
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From d536a40973710676f89fb60ed688fa9c335a7f5a Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn created
https://github.com/llvm/llvm-project/pull/125432
After splitting, all elements are created. The elements are
placed back into a concat_vectors. This change extends EltsFromConsecutiveLoads
to understand AtomicSDNode so that its concat_vectors can be
mapped to a B
https://github.com/jofrn edited https://github.com/llvm/llvm-project/pull/120598
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>From 4df72a297c3be02f7dc46fbb4f4dcf1cb69c21f1 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From f096c88041cc230ad66b40e4394563cbc696b7a6 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/Meinersbur edited
https://github.com/llvm/llvm-project/pull/125427
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None
>From 06b025db36dff8c1a3b0b22ae884d6506611f455 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Sun, 2 Feb 2025 18:48:32 +0100
Subject: [PATCH] Update ScopInliner to support NPM
---
polly/docs/Relea
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@@ -219,6 +220,54 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/nhaehnle commented:
Thank you for moving the insert point.
An analogous comment applies here like in the non-i1 case: it would be good to
cache the `MergedMask` register for re-use when the same `Inst` occurs with
multiple `UseInst`s.
https://github.com/llvm/llvm-project/pu
@@ -219,6 +220,54 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
return false;
}
+bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
+ MachineRegisterInfo::VRegAttrs BoolS1 = {ST->getBoolRC(), LLT::scalar(1)};
+ initializeLaneMaskRegisterAttributes
https://github.com/nhaehnle edited
https://github.com/llvm/llvm-project/pull/124299
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https://github.com/nhaehnle commented:
I haven't done a detailed review of the code, but from a high-level algorithmic
view this change already looks pretty reasonable to me.
https://github.com/llvm/llvm-project/pull/124298
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@@ -188,6 +190,35 @@ void
DivergenceLoweringHelper::constrainAsLaneMask(Incoming &In) {
In.Reg = Copy.getReg(0);
}
+void replaceUsesOfRegInInstWith(Register Reg, MachineInstr *Inst,
+Register NewReg) {
+ for (MachineOperand &Op : Inst->opera
llvmbot wrote:
@llvm/pr-subscribers-clang-modules
@llvm/pr-subscribers-clang
Author: Matheus Izvekov (mizvekov)
Changes
This rename follows the proposed wording in P3310R5, which introduces the term
'strict pack match' to refer to the same thing.
---
Patch is 33.18 KiB, truncated to 20.
https://github.com/mizvekov created
https://github.com/llvm/llvm-project/pull/125418
This rename follows the proposed wording in P3310R5, which introduces the term
'strict pack match' to refer to the same thing.
>From 772973a841ad739172a9f23bc1403924eea4cba8 Mon Sep 17 00:00:00 2001
From: Math
phoebewang wrote:
Ping @tstellar, any reason this was missing in rc1 release?
https://github.com/llvm/llvm-project/pull/125057
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>From f816bd39f6986825e338198fce8747939ab1c882 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Thu, 30 Jan 2025 21:13:49 +0800
Subject: [PATCH] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2
to
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: NAKAMURA Takumi (chapuni)
Changes
A warning "contains an operation with a nested boolean expression." is no
longer emitted. At the moment, split expressions are treated as individual
Decisions.
---
Full diff: https://github.com/llvm/llvm
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125413
A warning "contains an operation with a nested boolean expression." is no
longer emitted. At the moment, split expressions are treated as individual
Decisions.
>From c56ecc30e9fd1a674073e362fbfcc6b43f2f52e2 Mo
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: NAKAMURA Takumi (chapuni)
Changes
MCDCCondBitmapAddr is moved from `CodeGenFunction` into `MCDCState` and created
for each Decision.
In `maybeCreateMCDCCondBitmap`, Allocate bitmaps for all valid Decisions and
emit them order by ID, to p
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125411
MCDCCondBitmapAddr is moved from `CodeGenFunction` into `MCDCState` and created
for each Decision.
In `maybeCreateMCDCCondBitmap`, Allocate bitmaps for all valid Decisions and
emit them order by ID, to prevent
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: NAKAMURA Takumi (chapuni)
Changes
`MCDCLogOpStack` is used only for detection of the Decision root. It can be
detected with `MCDC::State::DecisionByStmt`.
---
Full diff: https://github.com/llvm/llvm-project/pull/125410.diff
4 Fi
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125410
`MCDCLogOpStack` is used only for detection of the Decision root. It can be
detected with `MCDC::State::DecisionByStmt`.
>From 8eff226c98bdcfcd1366120699a42e0c4c73375c Mon Sep 17 00:00:00 2001
From: NAKAMURA Ta
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: NAKAMURA Takumi (chapuni)
Changes
- Get rid of the old `DecisionStack` and dissolve it into push/pop `CurCondIDs`
in `VisitBin`, since `VisitBin` is recursive.
- Introduce the new `DecisionStack` with `DecisionState` to handle the current
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125409
- Get rid of the old `DecisionStack` and dissolve it into push/pop `CurCondIDs`
in `VisitBin`, since `VisitBin` is recursive.
- Introduce the new `DecisionStack` with `DecisionState` to handle the current
`Dec
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: NAKAMURA Takumi (chapuni)
Changes
In the current implementation, `!(a || b) && c` was not treated as one
Decision with three terms.
Fixes #124563
---
Full diff: https://github.com/llvm/llvm-project/pull/125406.diff
6 Files Affected:
-
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125406
In the current implementation, `!(a || b) && c` was not treated as one Decision
with three terms.
Fixes #124563
>From f2cf50e10b59d7d461967baef4d589c9282d0f6d Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Da
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: NAKAMURA Takumi (chapuni)
Changes
Fixes #124565
---
Full diff: https://github.com/llvm/llvm-project/pull/125405.diff
4 Files Affected:
- (modified) clang/include/clang/AST/IgnoreExpr.h (+9)
- (modified) clang/lib/CodeGen/CodeGe
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: NAKAMURA Takumi (chapuni)
Changes
Fixes #124565
---
Full diff: https://github.com/llvm/llvm-project/pull/125405.diff
4 Files Affected:
- (modified) clang/include/clang/AST/IgnoreExpr.h (+9)
- (modified) clang/lib/CodeGen/CodeGenFunctio
https://github.com/chapuni created
https://github.com/llvm/llvm-project/pull/125405
Fixes #124565
>From f70a6c8686617963c55854c2d8c6fa8607ca0806 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 2 Feb 2025 22:10:25 +0900
Subject: [PATCH] [MC/DC] Handle __builtin_expect as if parenthses
https://github.com/nikic edited https://github.com/llvm/llvm-project/pull/87573
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llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport 1af627b592dd15bbe58136f902ced46251fc344d
Requested by: @dtcxzyw
---
Full diff: https://github.com/llvm/llvm-project/pull/125398.diff
2 Files Affected:
- (modified) llvm/lib/Analysis/Instruction
llvmbot wrote:
@llvm/pr-subscribers-llvm-analysis
Author: None (llvmbot)
Changes
Backport 1af627b592dd15bbe58136f902ced46251fc344d
Requested by: @dtcxzyw
---
Full diff: https://github.com/llvm/llvm-project/pull/125398.diff
2 Files Affected:
- (modified) llvm/lib/Analysis/InstructionSi
llvmbot wrote:
@nikic What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/125398
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https://github.com/llvm/llvm-project/pull/125398
Backport 1af627b592dd15bbe58136f902ced46251fc344d
Requested by: @dtcxzyw
>From 1e0bfeed4d8f888cf5ddbeeeb9af13a047b67fa5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 2 Feb 2025 19:04:23 +0800
Subject
https://github.com/nikic requested changes to this pull request.
Missing LangRef specification.
More generally, a lot of context seems to be missing here. I see you link two
RFCs from 2021, neither of which appear to have received a response, and
neither of which actually describe the proposed
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