@@ -1627,14 +1627,31 @@ class CodeGenFunction : public CodeGenTypeCache {
}
void markStmtMaybeUsed(const Stmt *S) { PGO.markStmtMaybeUsed(S); }
+ enum CounterForIncrement {
ornata wrote:
doxygen comment would be useful here
https://github.com/llvm/llvm-
@@ -1627,14 +1627,31 @@ class CodeGenFunction : public CodeGenTypeCache {
}
void markStmtMaybeUsed(const Stmt *S) { PGO.markStmtMaybeUsed(S); }
+ enum CounterForIncrement {
ornata wrote:
is the meaning of "exec counter" and "skip counter" defined anywher
@@ -884,6 +884,9 @@ struct CounterCoverageMappingBuilder
/// The map of statements to count values.
llvm::DenseMap &CounterMap;
+ CounterExpressionBuilder::SubstMap MapToExpand;
ornata wrote:
MapToExpand could use a doxygen comment explaining what it is
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 9f9ddaae799bc8a6464df81e215ca2cbefee0719 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 48d128350edc71ddca5892552dadf076be766f94 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 09:21:11 -0800
Subject: [PATCH] [RISCV] Change linker job in Baremetal toolchain object to
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/122049
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https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/122049
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
AMDGPU: Reduce 64-bit add width if high bits are known 0
If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.
Add case: https://alive2.llv
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/122049
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/122049?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/122049
AMDGPU: Reduce 64-bit add width if high bits are known 0
If one of the inputs has all 0 bits, the low part cannot
carry and we can just pass through the original value.
Add case: https://alive2.llvm.org/ce/z/TNc
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113113
>From 16e2bb8b73bcde1c2618bb358a905a9f463c1217 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 16:24:26 +0900
Subject: [PATCH 1/3] [Coverage][Single] Enable Branch coverage for `BinLAnd`
a
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113113
>From 16e2bb8b73bcde1c2618bb358a905a9f463c1217 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 16:24:26 +0900
Subject: [PATCH 1/3] [Coverage][Single] Enable Branch coverage for `BinLAnd`
a
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113111
>From 3ea6383e2142889550f37389dfaaee81e5ae7d9c Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 15:15:03 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for IfStmt
---
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113110
>From 744c5b634de08f9214c82d6fcfde7179bc4edfb0 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Sun, 20 Oct 2024 14:46:07 +0900
Subject: [PATCH 1/5] [Coverage][Single] Enable Branch coverage for CondOp
---
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113109
>From 5d19c77551c6fc585d1b15c4c2a71c3c3f99ef8a Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Fri, 18 Oct 2024 09:33:51 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for loop
statem
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/113112
>From ec05cc37e1177f06c9a44a1e39dadc9306cc5c68 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 21 Oct 2024 08:09:31 +0900
Subject: [PATCH 1/4] [Coverage][Single] Enable Branch coverage for SwitchStmt
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/120930
>From 5e460594c8a2550c38c759b2e6f1c5dc4152f820 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Thu, 17 Oct 2024 22:15:12 +0900
Subject: [PATCH 01/10] [Coverage] Make additional counters available for
Branc
Author: Vitaly Buka
Date: 2025-01-07T15:59:59-08:00
New Revision: 5d47208ffaf367a2bd40ebe8a197315e5b03b66d
URL:
https://github.com/llvm/llvm-project/commit/5d47208ffaf367a2bd40ebe8a197315e5b03b66d
DIFF:
https://github.com/llvm/llvm-project/commit/5d47208ffaf367a2bd40ebe8a197315e5b03b66d.diff
L
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/121820
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https://github.com/llvm/llvm-project/pull/121820
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@@ -650,48 +650,127 @@ literal types are uniqued in recent versions of LLVM.
.. _nointptrtype:
-Non-Integral Pointer Type
--
+Non-Integral and Unstable Pointer Types
+---
-Note: non-integral pointer types are a wor
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/7] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/6] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses
kparzysz wrote:
The build failures are unrelated to the code. There is some flaky testcase
that causes the breakage.
https://github.com/llvm/llvm-project/pull/121817
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https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/5] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses
@@ -59,4 +97,39 @@
// RUN: | FileCheck -check-prefix=CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX %s
// CXX-ARM-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/../../../../armv6m-none-eabi/include/c++/v1"
-// CXX-ARM-BA
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/4] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121815
>From 215c7e6133bf07d005ac7483b8faf797e319a1fa Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH] [flang][OpenMP] Parsing context selectors for METADIRECTI
https://github.com/kparzysz updated
https://github.com/llvm/llvm-project/pull/121817
>From 5f534c559ca1bb7911b484264582d1a5078bdcb8 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek
Date: Thu, 12 Dec 2024 15:26:26 -0600
Subject: [PATCH 1/4] [flang][OpenMP] Parse WHEN, OTHERWISE, MATCH clauses
@@ -151,3 +151,17 @@ define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr,
ret void
}
+define <2 x ptr> @atomic_vec2_ptr_align(ptr %x) nounwind {
+; CHECK-LABEL: @atomic_vec2_ptr_align(
+; CHECK-NEXT:[[TMP1:%.*]] = call i128 @__atomic_load_16(ptr [[X:%.*]], i32
2)
@@ -2060,9 +2060,28 @@ bool AtomicExpandImpl::expandAtomicOpToLibcall(
I->replaceAllUsesWith(V);
} else if (HasResult) {
Value *V;
-if (UseSizedLibcall)
- V = Builder.CreateBitOrPointerCast(Result, I->getType());
-else {
+if (UseSizedLibcall) {
+
@@ -151,3 +151,17 @@ define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr,
ret void
}
+define <2 x ptr> @atomic_vec2_ptr_align(ptr %x) nounwind {
+; CHECK-LABEL: @atomic_vec2_ptr_align(
+; CHECK-NEXT:[[TMP1:%.*]] = call i128 @__atomic_load_16(ptr [[X:%.*]], i32
2)
@@ -2726,15 +2740,11 @@ class OpenMPIRBuilder {
///
/// \param Loc The insert and source location description.
/// \param IsSPMD Flag to indicate if the kernel is an SPMD kernel or not.
- /// \param MinThreads Minimal number of threads, or 0.
- /// \param MaxThreads Max
@@ -146,11 +149,137 @@ static cl::opt SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::
@@ -0,0 +1,43 @@
+//==- RegAllocGreedyPass.h --- greedy register allocator pass
--*-C++-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -146,11 +149,137 @@ static cl::opt SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121831
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https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121830
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 824839c706f91d2d23c43fdd3ab1d930434112a3 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From 3a0559c3db5e9fa366d17d461028223e418f2e66 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 09:21:11 -0800
Subject: [PATCH] [RISCV] Change linker job in Baremetal toolchain object to
@@ -357,3 +391,21 @@ DevelopmentModePriorityAdvisor::getPriority(const
LiveInterval &LI) const {
}
#endif // #ifdef LLVM_HAVE_TFLITE
+
+void RegAllocPriorityAdvisorAnalysis::initializeMLProvider(
+RegAllocPriorityAdvisorProvider::AdvisorMode Mode, LLVMContext &Ctx) {
+ i
@@ -20,76 +20,138 @@
using namespace llvm;
-static cl::opt Mode(
+static cl::opt Mode(
"regalloc-enable-priority-advisor", cl::Hidden,
-cl::init(RegAllocPriorityAdvisorAnalysis::AdvisorMode::Default),
+cl::init(RegAllocPriorityAdvisorProvider::AdvisorMode::Defaul
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From 71f80fc3a116a28319153127cdbcb0086e64b064 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 634c858c8b4008010ffecdcd9b0d55c579bae3f3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
ll
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 4fcfde3d0081ac64e76a443d02723c32b87c1bc9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From c35bc75339bd5494ff223c2fc3f0c5631d7ebab4 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llv
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/118462
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From 231749a31aaa89a92a810c6356a006b68bb0f3a0 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From b7da349a13bff1055ae0bca795c922cf41cbd290 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
ll
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 4b62a383d0f187c72e64ccf952a3c78150c743a5 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From c5bc17bd90f05e3adb9867c65c93f4a9f510b02e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 50b6c21960a7cba5a757eb3301ca568bc075ec83 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
ll
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From d165ddda7caba11c2f268313706fbec6fa883ee3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119181
>From 0cff04bc8e3745ac627796faaf61e77c9dfd9ff6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 9 Dec 2024 07:58:48 +
Subject: [PATCH] Spiller: Deatach legacy pass and supply analyses instead
---
llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From c5bc17bd90f05e3adb9867c65c93f4a9f510b02e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/117309
>From 04586196b610c1348bfe5fbdd67b9faa43431b43 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 22 Nov 2024 09:31:50 +
Subject: [PATCH 1/8] [CodeGen][NewPM] Port RegAllocEvictionAdvisor analysis to
NP
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