[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

@@ -2701,7 +2701,42 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, const parser::OpenMPDeclareMapperConstruct &declareMapperConstruct) { - TODO(converter.getC

[llvm-branch-commits] [llvm] [RISCV] Add FeatureDisableLatencySchedHeuristic (PR #115858)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Match and Select BITOP3 on gfx950 (PR #117843)

arsenm wrote: ### Merge activity * **Nov 27, 1:23 AM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117843). https://github.com/llvm/llvm-project/pull/117843 _

[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

@@ -2701,7 +2701,42 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, const parser::OpenMPDeclareMapperConstruct &declareMapperConstruct) { - TODO(converter.getC

[llvm-branch-commits] [llvm] AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard (PR #117844)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117844 >From 986bb31b7d8e9a6ee659e66ccaa7c8a2b67269df Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 22 Jul 2024 04:59:08 -0400 Subject: [PATCH] AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard gfx950 SP

[llvm-branch-commits] [llvm] AMDGPU: Match and Select BITOP3 on gfx950 (PR #117843)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117843 >From ffac062d560a4624a911af7061a7f7b12b4c16f5 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 2 Mar 2023 14:10:01 -0800 Subject: [PATCH] AMDGPU: Match and Select BITOP3 on gfx950 Co-authored-by:

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117822 >From 7ce35330ba1fc60e3236451b8853679b566fddbf Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Thu, 11 Jul 2024 05:12:42 -0400 Subject: [PATCH] AMDGPU: Allocate different registers for vdst & src in v_cvt_sca

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117825). https://github.com/llvm/llvm-project/pull/117825

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117822). https://github.com/llvm/llvm-project/pull/117822

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117823). https://github.com/llvm/llvm-project/pull/117823

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117826). https://github.com/llvm/llvm-project/pull/117826

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117824). https://github.com/llvm/llvm-project/pull/117824

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

arsenm wrote: ### Merge activity * **Nov 26, 11:16 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117821). https://github.com/llvm/llvm-project/pull/117821

[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

wangpc-pp wrote: Thanks for evaluating this! The data is very helpful! @michaelmaitland > Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly > justify which cases this is profitable and figure out how to selectively > enable only in profitable cases. I agree with @m

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117825 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117825 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117824 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117824 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117823 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117823 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117822 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117822 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117821 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117821 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117827 >From 5241f294949f52ec4678ea2635fc550ca19e8aad Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 15 Nov 2024 08:13:53 -0800 Subject: [PATCH] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 --- llvm/lib/T

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (PR #117744)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117744). https://github.com/llvm/llvm-project/pull/117744 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Patch is 256.37 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117827.diff 35 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsAMD

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Verify the register widths of the corresponding operands match the floating point format expected size. --- Patch is 22.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117826 >From e9df017c277f38ff299d45a444e34e7af79401bb Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 17 Jul 2024 19:36:13 +0400 Subject: [PATCH] AMDGPU: Verify f8f6f4 formats in assembler Verify the register

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117825 >From ff1c11253fc5f220ddc92f1733d2151d2e5c54df Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 18 Jun 2024 23:30:05 -0400 Subject: [PATCH] AMDGPU/clang: Add global_load_lds size check support for gfx950 C

[llvm-branch-commits] [clang] [llvm] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Patch is 212.23 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117825.diff 28 Files Affected: -

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Patch is 23.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117824.diff 10 Files Affected: -

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Patch is 49.32 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117821.diff 8 Files Affected: - (

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117824 >From 5a11a724489d190b535af1b73a50bdc44c62e812 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Wed, 5 Jun 2024 14:16:20 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instr

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117823 >From f76165bd1ab51e40c73abe52b1eebcfd8dfa0d8c Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 20 May 2024 04:39:24 -0400 Subject: [PATCH] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gf

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117822 >From bbc7178519e6bbb7477bc66bb8e10685d4245381 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Thu, 11 Jul 2024 05:12:42 -0400 Subject: [PATCH] AMDGPU: Allocate different registers for vdst & src in v_cvt_sca

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117821 >From b26cbd2043132438fea529b8ee3eb91ec8f9c064 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 4 Jun 2024 16:31:19 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117822?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117827?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117827 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Pravin Jagtap --- Patch is 25.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117823.diff 11 Files Affected:

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117825 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117824 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117823 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes For multipass instructions, overlap on VDST and SRC’s would result in HW race & undefined results. Co-authored-by: Pravin Jagtap --- Patch is 68.02 KiB, truncated to 20.00

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117822 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117821 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for v_cvt_scalef32_sr instructions (PR #117820)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117820 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117826?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117823?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117824?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117825?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117821?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for v_cvt_scalef32_sr instructions (PR #117820)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117820?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (PR #117827)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117827 None >From 5f45ccd6f0f867fe087a9ace290c41b2f57fc760 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 15 Nov 2024 08:13:53 -0800 Subject: [PATCH] AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 --- llvm

[llvm-branch-commits] [llvm] AMDGPU: Verify f8f6f4 formats in assembler (PR #117826)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117826 Verify the register widths of the corresponding operands match the floating point format expected size. >From 6a5a2df498a151d1e0ef8dc41e2d00c515b4f637 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 17

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for v_cvt_scalef32_sr instructions (PR #117820)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117820 Co-authored-by: Shilei Tian >From aeac3cde571223700deab8800fc1943989d7f440 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 4 Jun 2024 13:59:28 -0400 Subject: [PATCH] AMDGPU: Add support for v_cvt_scalef32

[llvm-branch-commits] [clang] AMDGPU/clang: Add global_load_lds size check support for gfx950 (PR #117825)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117825 Co-authored-by: Shilei Tian >From bebc41c78dbf24e10bcd053c555035397f609efb Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 18 Jun 2024 23:30:05 -0400 Subject: [PATCH] AMDGPU/clang: Add global_load_lds siz

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (PR #117824)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117824 Co-authored-by: Shilei Tian >From e511ff9110c445d9b2971bbe43c946d75afaaeff Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Wed, 5 Jun 2024 14:16:20 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (PR #117823)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117823 Co-authored-by: Pravin Jagtap >From 4e8c398e6138f862d919ed4f54fd02ef88ea8d4f Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Mon, 20 May 2024 04:39:24 -0400 Subject: [PATCH] AMDGPU: Add builtins & codegen su

[llvm-branch-commits] [llvm] AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (PR #117822)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117822 For multipass instructions, overlap on VDST and SRC’s would result in HW race & undefined results. Co-authored-by: Pravin Jagtap >From 418ffe2eedd620829043e7585371464ec2dd44c7 Mon Sep 17 00:00:00 2001 From: Pra

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117821)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117821 Co-authored-by: Shilei Tian >From 3e035374106b4c8d510319dcfdd65362537ccef6 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 4 Jun 2024 16:31:19 -0400 Subject: [PATCH] AMDGPU: Builtin & CodeGen support for

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117795). https://github.com/llvm/llvm-project/pull/117795 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117794). https://github.com/llvm/llvm-project/pull/117794 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (PR #117743)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117743). https://github.com/llvm/llvm-project/pull/117743 _

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117796). https://github.com/llvm/llvm-project/pull/117796 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (PR #117745)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117745). https://github.com/llvm/llvm-project/pull/117745 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (PR #117747)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117747). https://github.com/llvm/llvm-project/pull/117747 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117793). https://github.com/llvm/llvm-project/pull/117793 _

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117797). https://github.com/llvm/llvm-project/pull/117797 _

[llvm-branch-commits] [clang] [llvm] Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (PR #117742)

arsenm wrote: ### Merge activity * **Nov 26, 7:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117742). https://github.com/llvm/llvm-project/pull/117742 _

[llvm-branch-commits] [clang] [flang] [lld] [llvm] [Flang] LLVM_ENABLE_RUNTIMES=flang-rt (PR #110217)

h-vetinari wrote: > Compiling this on linux with GCC/gfortran (after fixing > [this](https://github.com/llvm/llvm-project/pull/110298#discussion_r1849519429)) > currently runs into the following for me @Meinersbur, could you let me know if/once you think this should be fixed, then I'll give i

[llvm-branch-commits] [libc] 590814b - Revert "[libc] Implement process_mrelease. (#117503)"

Author: lntue Date: 2024-11-26T18:02:08-05:00 New Revision: 590814b3d773187ca1fec7de170bde470a00a875 URL: https://github.com/llvm/llvm-project/commit/590814b3d773187ca1fec7de170bde470a00a875 DIFF: https://github.com/llvm/llvm-project/commit/590814b3d773187ca1fec7de170bde470a00a875.diff LOG: Re

[llvm-branch-commits] [clang] 638427b - Revert "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge (…"

Author: Thurston Dang Date: 2024-11-26T14:27:18-08:00 New Revision: 638427b08f7308f388b7f0bdaf426ca1f58e1b18 URL: https://github.com/llvm/llvm-project/commit/638427b08f7308f388b7f0bdaf426ca1f58e1b18 DIFF: https://github.com/llvm/llvm-project/commit/638427b08f7308f388b7f0bdaf426ca1f58e1b18.diff

[llvm-branch-commits] [flang] [flang][OpenMP] Use new modifiers with AFFINITY/ALIGNED/DEVICE (PR #117786)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/117786 >From 09b1270faf2dc5125c36c7f4cc246b3a922d5b08 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Mon, 25 Nov 2024 14:55:37 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Use new modifiers with AFFINITY/ALIG

[llvm-branch-commits] [flang] [flang][OpenMP] Rename some `Type` members in OpenMP clauses (PR #117784)

https://github.com/kparzysz updated https://github.com/llvm/llvm-project/pull/117784 >From ee00ecdc5a8b342c80ef34a8e1a1c8bb91855ab8 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 26 Nov 2024 09:01:49 -0600 Subject: [PATCH 1/2] [flang][OpenMP] Rename some `Type` members in OpenMP

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117795 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117795 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117793 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117794 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (PR #117794)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117794 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (PR #117793)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117793 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (PR #117795)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117795.diff 5 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmPar

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (PR #117798)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Patch is 32.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/117798.diff 8 Files Affected: - (

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (PR #117797)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117797.diff 5 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+3) -

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Co-authored-by: Shilei Tian --- Full diff: https://github.com/llvm/llvm-project/pull/117796.diff 7 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+10) - (mo

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (PR #117796)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

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