[llvm-branch-commits] [mlir] [mlir][LLVM] `LLVMTypeConverter`: Tighten materialization checks (PR #116532)

https://github.com/matthias-springer updated https://github.com/llvm/llvm-project/pull/116532 >From 4e4a5c81a1c45c8d4fbadacd67fa5439231e912e Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 23 Nov 2024 08:22:13 +0100 Subject: [PATCH 1/2] [mlir][Func] Delete `DecomposeCallGraphTypes.c

[llvm-branch-commits] [mlir] [mlir][LLVM] `LLVMTypeConverter`: Tighten materialization checks (PR #116532)

https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/116532 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [mlir] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp` (PR #117424)

https://github.com/matthias-springer updated https://github.com/llvm/llvm-project/pull/117424 >From 4e4a5c81a1c45c8d4fbadacd67fa5439231e912e Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 23 Nov 2024 08:22:13 +0100 Subject: [PATCH] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp`

[llvm-branch-commits] [mlir] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp` (PR #117424)

https://github.com/matthias-springer updated https://github.com/llvm/llvm-project/pull/117424 >From 5d6e8e449e9e4900cf250f0a432dc4c63b7f0470 Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 23 Nov 2024 08:22:13 +0100 Subject: [PATCH] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp`

[llvm-branch-commits] [mlir] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp` (PR #117424)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff 47e321a15b9d4e7fad5422f91fcab46781bb47c8 f8514c8715b677cbbd42627e1d2afba3d81a9d72 --e

[llvm-branch-commits] [mlir] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp` (PR #117424)

llvmbot wrote: @llvm/pr-subscribers-mlir Author: Matthias Springer (matthias-springer) Changes `DecomposeCallGraphTypes.cpp` was a workaround around missing 1:N support in the dialect conversion. Now that 1:N support was added, the workaround can be deleted. The test remains in place, as

[llvm-branch-commits] [mlir] [mlir][Func] Delete `DecomposeCallGraphTypes.cpp` (PR #117424)

https://github.com/matthias-springer created https://github.com/llvm/llvm-project/pull/117424 `DecomposeCallGraphTypes.cpp` was a workaround around missing 1:N support in the dialect conversion. Now that 1:N support was added, the workaround can be deleted. The test remains in place, as an exa

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117411 >From baa4dc15207c23d396e3ec3da6b4a88068899f90 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Nov 2024 18:40:25 -0800 Subject: [PATCH] AMDGPU: Use isWave[32|64] instead of comparing size value ---

[llvm-branch-commits] [llvm] AMDGPU: Remove wavefrontsize64 feature from dummy target (PR #117410)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117410 >From a9b9b652bf14cf9da1521caad4a5ff4a9a8bc7b0 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Nov 2024 17:21:18 -0800 Subject: [PATCH 1/2] AMDGPU: Remove wavefrontsize64 feature from dummy target Th

[llvm-branch-commits] [llvm] AMDGPU: Remove wavefrontsize64 feature from dummy target (PR #117410)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/117410 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes You cannot adjust the disassembler's subtarget. llvm-mc passes the originally constructed MCSubtargetInfo around, rather than querying the pointer in the disassembler instance. --- Full diff: https:

[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117422 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Remove wavefrontsize64 feature from dummy target (PR #117410)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/117410 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117422 You cannot adjust the disassembler's subtarget. llvm-mc passes the originally constructed MCSubtargetInfo around, rather than querying the pointer in the disassembler instance. >From bccd64648635ab9cdab25bfe3c910

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117411 >From 7dfd593219269aec94cf2830997ecc3e749202ec Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Nov 2024 18:40:25 -0800 Subject: [PATCH] AMDGPU: Use isWave[32|64] instead of comparing size value ---

[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117422?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (PR #117417)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117417?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (PR #117287)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117287 >From 31815a006d98594bd1ac90b81ca1d80cdb512ab5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 14:41:11 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard --

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (PR #117418)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117418?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (PR #117418)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (PR #117418)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authore

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (PR #117418)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117418 OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (PR #117418)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117418 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (PR #117417)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d] where, c & d i.e. O

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (PR #117417)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117417 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (PR #117417)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117417 OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z] where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read. OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d] where, c & d i.e. OPS

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117384 >From 3a197551c721eac438fe6f7663b20e2cabee4c90 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sun, 7 Apr 2024 01:57:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117383 >From 3ee9b05d97324ddc6146524391ebb909efbf Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117382 >From 10237f9ca9aabcb9417450db0d28d097bbb82c2b Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117381 >From 53e58c2f075903f6e83e182e14d138dc4ca3ca06 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 07:19:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117380 >From 3324376d20cb7dc9f6f5250a09b0b0f44362cdff Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 02:35:49 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117379 >From f2e1659bb07000c319ebfab810b5d85c078db1a8 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 Co-authored-b

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117378 >From 9251dafd6d18cbd65b5c2ca2c4960e6b58436362 Mon Sep 17 00:00:00 2001 From: Sirish Pande Date: Wed, 7 Feb 2024 10:12:03 -0600 Subject: [PATCH] AMDGPU: Add support for load transpose instructions for gfx950 Th

[llvm-branch-commits] [llvm] AMDGPU: Handle vcmpx+permalane gfx950 hazard (PR #117286)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117286 >From 333e4d806d51da1858eb428e58fbf58b2d554edf Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 13:45:22 +0530 Subject: [PATCH] AMDGPU: Handle vcmpx+permalane gfx950 hazard Confusingly, this

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N `matchAndRewrite` overload (PR #116470)

https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/116470 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N `matchAndRewrite` overload (PR #116470)

https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/116470 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117383 >From 717812c8de83e42c34c7ceef0eb2dc82980b875f Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117384 >From 58fde3075c3f8d020a181456a5a270231767e4c1 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sun, 7 Apr 2024 01:57:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117382 >From 68282297a4eddeb5c71c2b0757bfd759f6813f25 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117381 >From 9f7e7fd55d71afc3b12e1fbb947a29c95b2d1d0d Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 07:19:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117380 >From 2cdbe55dd974940bf89dcecb7bf9a66fb9febe42 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 02:35:49 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117379 >From 2d7a1ca9803e94d4dda0594f52deb983c40dd14b Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 Co-authored-b

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117378 >From e32d731b9c2c4409f00e1b738f93c7b2407212ca Mon Sep 17 00:00:00 2001 From: Sirish Pande Date: Wed, 7 Feb 2024 10:12:03 -0600 Subject: [PATCH] AMDGPU: Add support for load transpose instructions for gfx950 Th

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (PR #117287)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117287 >From 4ad9760c6300afbded15ab14f542f47e02d2efef Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 14:41:11 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard --

[llvm-branch-commits] [llvm] AMDGPU: Handle vcmpx+permalane gfx950 hazard (PR #117286)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117286 >From d3de92249f924b1d518c366d881a0ac59eedc58b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 13:45:22 +0530 Subject: [PATCH] AMDGPU: Handle vcmpx+permalane gfx950 hazard Confusingly, this

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117262 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

arsenm wrote: ### Merge activity * **Nov 22, 11:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117262). https://github.com/llvm/llvm-project/pull/117262

[llvm-branch-commits] [llvm] AMDGPU: Define new sched model for gfx950 (PR #117261)

arsenm wrote: ### Merge activity * **Nov 22, 11:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117261). https://github.com/llvm/llvm-project/pull/117261

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (PR #117284)

arsenm wrote: ### Merge activity * **Nov 22, 11:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117284). https://github.com/llvm/llvm-project/pull/117284

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

arsenm wrote: ### Merge activity * **Nov 22, 11:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117283). https://github.com/llvm/llvm-project/pull/117283

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

arsenm wrote: ### Merge activity * **Nov 22, 11:08 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117263). https://github.com/llvm/llvm-project/pull/117263

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (PR #117284)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117284 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (PR #117284)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117284 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117262 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/jhuber6 approved this pull request. LG https://github.com/llvm/llvm-project/pull/117411 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/117411.diff 3 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-2) - (modified) llvm/lib/Target/AMDGPU/SIInstrI

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117411?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117411 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117411 None >From 7016169b68c98fbf4e9467483a9c2ca4fe7c6dcc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Nov 2024 18:40:25 -0800 Subject: [PATCH] AMDGPU: Use isWave[32|64] instead of comparing size value

[llvm-branch-commits] [llvm] d69790b - Revert "[MemProf] Use radix tree for alloc contexts in bitcode summaries (#11…"

Author: Teresa Johnson Date: 2024-11-22T14:57:26-08:00 New Revision: d69790b481cea9196b7b59f542c8771f3103b425 URL: https://github.com/llvm/llvm-project/commit/d69790b481cea9196b7b59f542c8771f3103b425 DIFF: https://github.com/llvm/llvm-project/commit/d69790b481cea9196b7b59f542c8771f3103b425.diff

[llvm-branch-commits] [lld] [lld][Hexagon] Fix R_HEX_B22_PCREL range checks (#115925) (PR #116906)

https://github.com/SidManning approved this pull request. https://github.com/llvm/llvm-project/pull/116906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117384 >From d5c3e0b8dd48841b1b23bb847919683d9a5d8506 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sun, 7 Apr 2024 01:57:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117382 >From bad2d8e5dcac64128c8e73d0b9752cb6bfe17620 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117383 >From a009325974e7d0cffbf288d2dd9b4d3d2e392007 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117381 >From cff4def955447d2adaff3caebc323f23320a3e73 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 07:19:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117380 >From d34c2cc46c6adc0e9ce80ce92f69e755e66774ed Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 02:35:49 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117379 >From 2bb646ca3045532b382a8c6d0db9b5ffe6bd4d2e Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 Co-authored-b

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117378 This patch support for intrinsics in clang, as well as assembly instructions in the backend. Co-authored-by: Sirish Pande >From 5806ee7ef05a77aee37bb93de6eeb223dd0186fa Mon Sep 17 00:00:00 2001 From: Sirish Pan

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117379 Co-authored-by: Pravin Jagtap >From 26772728d84c8cd247defa8a73448369ead9032a Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117382 OPSEL[3] selects low/high 16 bits of dest write. Co-authored-by: Pravin Jagtap >From 006e95f01c5de40a1a328c0d74642b8eced70414 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 S

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117384 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117262 >From a444594bee500951ff23d7745e19abdb22bc1019 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 15:01:08 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117379.diff 9 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+11-1) - (modified

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117380 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL[0] selects srcword to read. Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117383.diff 3 Files Affected: - (modified) llvm/l

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL[3] selects low/high 16 bits of dest write. Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117382.diff 3 Files Affected: - (m

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-by: Pravin Jagtap ---

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117383 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117382?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] i

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117382 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117383?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117381?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff 5806ee7ef05a77aee37bb93de6eeb223dd0186fa 26772728d84c8cd247defa8a73448369ead9032a --e

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117384?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117383 OPSEL[0] selects srcword to read. Co-authored-by: Pravin Jagtap >From a4c577bce86a5c827fb5e4c215e28189b8c8722e Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH]

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117381 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117384 OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-by: Pravin Jagtap >From 7f0c00c5714c8051de48b15

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117381 OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes This patch support for intrinsics in clang, as well as assembly instructions in the backend. Co-authored-by: Sirish Pande --- Patch is 28.39 KiB, truncated to 20.00 KiB belo

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117379 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117378?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117380?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117379?utm_source=stack-comment-downstack-mergeability-warning";

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