https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/112116
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Shilei Tian (shiltian)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/112116.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (+14-1)
- (added) llvm/test/CodeGen/AMDGPU/waitcnt
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/112116?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/112116
None
>From 59007297616ea2e11a06401b79833953318d42e0 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sat, 12 Oct 2024 23:58:25 -0400
Subject: [PATCH] [AMDGPU] Skip non-first termintors when forcing emit zero
var-const wrote:
@tru Thank you so much for accepting this! It looks like the CI is clean now.
https://github.com/llvm/llvm-project/pull/110677
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailm
@@ -112,42 +104,46 @@ entry:
define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize {
; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2:
; CHECK-ALIGNED-RV32: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16
-; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/107548
>From f21cfcfc90330ee3856746b6315a81a00313b0e0 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Fri, 6 Sep 2024 17:20:51 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
