@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
cdevadas wrote:
Mostly, the tests related to serialize options go in
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir.
Additionally, a negative test is required for th
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
cdevadas
https://github.com/var-const approved this pull request.
https://github.com/llvm/llvm-project/pull/110263
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llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Florian Mayer (fmayer)
Changes
We would put a placeholder in the tagp instruction, then replace all
uses of the original alloca with this, then replace the placeholder.
We use replaceUsesWithIf anyway, so it's easier to understan
https://github.com/fmayer created
https://github.com/llvm/llvm-project/pull/110337
We would put a placeholder in the tagp instruction, then replace all
uses of the original alloca with this, then replace the placeholder.
We use replaceUsesWithIf anyway, so it's easier to understand if we just
e
https://github.com/Meinersbur edited
https://github.com/llvm/llvm-project/pull/110217
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Author: Mehdi Amini
Date: 2024-09-27T20:33:29+02:00
New Revision: 53622333092cf61ebb3e39ecc6f7ccdb57d36453
URL:
https://github.com/llvm/llvm-project/commit/53622333092cf61ebb3e39ecc6f7ccdb57d36453
DIFF:
https://github.com/llvm/llvm-project/commit/53622333092cf61ebb3e39ecc6f7ccdb57d36453.diff
L
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 98c71d8b21084841d068fe77d117b506f1809e69
2216bfe4a07625d894accf5730a313a65d30a982 --e
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https://github.com/jayfoad approved this pull request.
LGTM, thanks! Please also backport to release/19.x.
https://github.com/llvm/llvm-project/pull/110256
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@@ -1911,7 +1911,7 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode
*Parent, SDValue Addr,
0);
}
- Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i16);
+ Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i32);
petar
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/110256
>From 2ea25b291ffdae0d3b9b6821199080f133de34c7 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 27 Sep 2024 13:59:31 +0200
Subject: [PATCH] AMDGPU: Fix inst-selection of large scratch offsets wi
https://github.com/ldionne edited
https://github.com/llvm/llvm-project/pull/109291
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ldionne wrote:
> I guess
> [6f6422f](https://github.com/llvm/llvm-project/commit/6f6422f4a2b8647a59936c131e50a79906d89510)
> and
> [cdd608b](https://github.com/llvm/llvm-project/commit/cdd608b8f0ce090b3568238387df368751bdbb5d)
> should also be cherry-picked. @tru @ldionne
This is now https:/
https://github.com/ldionne edited
https://github.com/llvm/llvm-project/pull/110162
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https://github.com/skatrak created
https://github.com/llvm/llvm-project/pull/110266
The `omp.section` operation is an outlier in that the block arguments it has
are defined by clauses on the required parent `omp.sections` operation.
This patch updates the definition of this operation introduci
https://github.com/ldionne created
https://github.com/llvm/llvm-project/pull/110259
None
>From 3be5c6921fbc46a3a4a6957b7b58c2398c8a8ce8 Mon Sep 17 00:00:00 2001
From: David Spickett
Date: Thu, 15 Aug 2024 08:14:13 +
Subject: [PATCH 1/2] [lldb][test] Mark sys_info zdump test unsupported on
https://github.com/ldionne created
https://github.com/llvm/llvm-project/pull/110263
We should have been checking against 1700, not 17000, which was a typo.
(cherry picked from commit 1eba87904b0cbaaee82cfdb835528b85d99320ef)
>From b1affedd7d2e4f2e13c3a2cbd8e3645fb5b9af0e Mon Sep 17 00:00:00 20
skatrak wrote:
PR stack:
- #109808
- #109809
- #109810
- #109811
- #110266
- #110267
https://github.com/llvm/llvm-project/pull/110266
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skatrak wrote:
PR stack:
- #109808
- #109809
- #109810
- #109811
- #110266
- #110267
https://github.com/llvm/llvm-project/pull/110267
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llvmbot wrote:
@llvm/pr-subscribers-flang-fir-hlfir
Author: Sergio Afonso (skatrak)
Changes
The main purpose of this patch is to centralize the logic for creating MLIR
operation entry blocks and for binding them to the corresponding symbols. This
minimizes the chances of mixing arguments
llvmbot wrote:
@llvm/pr-subscribers-mlir
Author: Sergio Afonso (skatrak)
Changes
The `omp.section` operation is an outlier in that the block arguments it has
are defined by clauses on the required parent `omp.sections` operation.
This patch updates the definition of this operation introd
https://github.com/skatrak created
https://github.com/llvm/llvm-project/pull/110267
The main purpose of this patch is to centralize the logic for creating MLIR
operation entry blocks and for binding them to the corresponding symbols. This
minimizes the chances of mixing arguments up for operat
https://github.com/ldionne edited
https://github.com/llvm/llvm-project/pull/110263
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llvmbot wrote:
@llvm/pr-subscribers-libcxx
Author: Louis Dionne (ldionne)
Changes
We should have been checking against 1700, not 17000, which was a typo.
(cherry picked from commit 1eba87904b0cbaaee82cfdb835528b85d99320ef)
---
Full diff: https://github.com/llvm/llvm-project/pull/110263.d
https://github.com/ldionne milestoned
https://github.com/llvm/llvm-project/pull/110263
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llvmbot wrote:
@llvm/pr-subscribers-libcxx
Author: Louis Dionne (ldionne)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/110259.diff
1 Files Affected:
- (modified)
libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/sys_info.zdump.pass.cpp
(+1-4)
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@@ -1911,7 +1911,7 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode
*Parent, SDValue Addr,
0);
}
- Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i16);
+ Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i32);
jayfo
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
Changes
Use i32 for offset instead of i16, this way it does not get interpreted
as negative 16 bit offset.
---
Full diff: https://github.com/llvm/llvm-project/pull/110256.diff
2 Files Affected:
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/110256
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https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/110256
Use i32 for offset instead of i16, this way it does not get interpreted
as negative 16 bit offset.
>From dcec93029eb0126761ed7521511294b9237591db Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110256?utm_source=stack-comment-downstack-mergeability-w
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/110229
None
>From 35536a8d4407f417d836b881fc7c389b295047c9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (Akshat-Oke)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/110229.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+15)
- (modified) llvm/lib/Target/AMDGPU/SIMa
https://github.com/Akshat-Oke ready_for_review
https://github.com/llvm/llvm-project/pull/110229
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https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/110108
>From af03c2af4aedd58ab941250d19c965ad774c4a46 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Wed, 25 Sep 2024 16:16:29 +0300
Subject: [PATCH] [AArch64] Generalize the instruction size checking in
Akshat-Oke wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110229?utm_source=stack-comment-downstack-mergeability-warnin
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