[llvm-branch-commits] [flang] [flang] Lower omp.workshare to other omp constructs (PR #101446)

2024-09-22 Thread via llvm-branch-commits
github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff d5fbe9c7482b87be295be03aafd5917dd7c17859 79ac7998609480d18be4ea3bc61b6c1c77089f70 --e

[llvm-branch-commits] [flang] [flang] Lower omp.workshare to other omp constructs (PR #101446)

2024-09-22 Thread Ivan R. Ivanov via llvm-branch-commits
https://github.com/ivanradanov updated https://github.com/llvm/llvm-project/pull/101446 >From e56dbd6a0625890fd9a3d6a62675e864ca94a8f5 Mon Sep 17 00:00:00 2001 From: Ivan Radanov Ivanov Date: Sun, 4 Aug 2024 22:06:55 +0900 Subject: [PATCH 1/3] [flang] Lower omp.workshare to other omp constructs

[llvm-branch-commits] [flang] [WIP][flang] Introduce HLFIR lowerings to omp.workshare_loop_nest (PR #104748)

2024-09-22 Thread Ivan R. Ivanov via llvm-branch-commits
https://github.com/ivanradanov updated https://github.com/llvm/llvm-project/pull/104748 >From 975a0d74c5ae81c69844b8bd089832ed53278477 Mon Sep 17 00:00:00 2001 From: Ivan Radanov Ivanov Date: Mon, 23 Sep 2024 15:07:48 +0900 Subject: [PATCH 1/4] Emit a proper error message for CFG in workshare

[llvm-branch-commits] [flang] [WIP][flang] Introduce HLFIR lowerings to omp.workshare_loop_nest (PR #104748)

2024-09-22 Thread Ivan R. Ivanov via llvm-branch-commits
https://github.com/ivanradanov updated https://github.com/llvm/llvm-project/pull/104748 >From e0ef194ecf8bf0e9c450ee11c244eb4450548aef Mon Sep 17 00:00:00 2001 From: Ivan Radanov Ivanov Date: Sun, 4 Aug 2024 17:33:52 +0900 Subject: [PATCH 1/2] Add workshare loop wrapper lowerings Bufferize tes

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

2024-09-22 Thread Walter Erquinigo via llvm-branch-commits
@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

2024-09-22 Thread Walter Erquinigo via llvm-branch-commits
@@ -1773,6 +1774,26 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters( OutStreamer->emitRawText(O.str()); } +/// Translate virtual register numbers in DebugInfo locations to their printed +/// encodings, as used by CUDA-GDB. +void NVPTXAsmPrinter::encodeDebugInfoRe

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

2024-09-22 Thread Walter Erquinigo via llvm-branch-commits
@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

2024-09-22 Thread Walter Erquinigo via llvm-branch-commits
@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis

[llvm-branch-commits] [llvm] [NVPTX] add support for encoding PTX registers for DWARF (PR #109495)

2024-09-22 Thread Walter Erquinigo via llvm-branch-commits
@@ -141,3 +142,47 @@ NVPTXRegisterInfo::getFrameLocalRegister(const MachineFunction &MF) const { static_cast(MF.getTarget()); return TM.is64Bit() ? NVPTX::VRFrameLocal64 : NVPTX::VRFrameLocal32; } + +void NVPTXRegisterInfo::clearDebugRegisterMap() const { + debugRegis