@@ -2241,6 +2247,11 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T)
const {
Align = ALIGN;
\
break;
#include "clang/Basic/AMDGPUTypes.def"
+#define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId) case Buil
@@ -757,7 +757,8 @@ void USRGenerator::VisitType(QualType T) {
case BuiltinType::OCLReserveID:
Out << "@BT@OCLReserveID"; break;
case BuiltinType::OCLSampler:
- Out << "@BT@OCLSampler"; break;
+ Out << "@BT@OCLSampler";
+ bre
@@ -1390,7 +1390,8 @@ void ASTContext::InitBuiltinTypes(const TargetInfo
&Target,
#include "clang/Basic/HLSLIntangibleTypes.def"
}
- if (Target.hasAArch64SVETypes()) {
+ if (Target.hasAArch64SVETypes() ||
python3kgae wrote:
Is this expected change for in
