[Lldb-commits] [compiler-rt] [libcxx] [mlir] [flang] [llvm] [clang-tools-extra] [clang] [libc] [lldb] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

dwpan wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? In Verilog/SystemVerilog language, the basic type is bit or bit vector, and length is arbitrary, insert/extract bits are common features in language. Introducing corresponding intrin

[Lldb-commits] [libcxx] [flang] [clang-tools-extra] [compiler-rt] [mlir] [llvm] [lldb] [libc] [clang] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

dwpan wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? In Verilog/SystemVerilog language, the basic type is bit or bit vector, and length is arbitrary, insert/extract bits are common features in language. Introducing corresponding intrins