DavidSpickett wrote:
@asb might have a IRSC-V Linux system handy to generate a core file from.
`lldb/test/API/functionalities/postmortem/elf-core/main_fpr.c` would cover GPR
and FPR, I think that's all we need here. It can be added to
`lldb/test/API/functionalities/postmortem/elf-core/TestLinu
JDevlieghere wrote:
> 1. This went in without tests, intentional?
Intentional insofar that I cannot share the core files I tested this against,
and that I don't know/have a way to generate one that I can check in.
> 2. Seems like a release note worthy feature.
I can add a release note 👍
htt
@@ -0,0 +1,185 @@
+//===-- RegisterInfos_riscv32.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
DavidSpickett wrote:
1. This went in without tests, intentional?
2. Seems like a release note worthy feature.
https://github.com/llvm/llvm-project/pull/115408
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JDevlieghere wrote:
@jasonmolenda Yes, my understanding is that the GPRs are 33*8=264 bytes for
riscv64 and 33*4=132 bytes for riscv32. The FPR start at offset 132.
https://github.com/llvm/llvm-project/pull/115408
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jasonmolenda wrote:
I see the latest update includes the necessary changes to ThreadElfCore, that
looks good.
I'm still curious what this code does when reading x0. The RegisterContext GPR
struct defines 32 elements, pc + x1-x31, and the offset of x0 would be the 33rd
element. But instead o
https://github.com/JDevlieghere edited
https://github.com/llvm/llvm-project/pull/115408
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https://github.com/llvm/llvm-project/pull/115408
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