[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

2025-03-07 Thread David Spickett via lldb-commits
https://github.com/DavidSpickett approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/130034 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

2025-03-07 Thread David Spickett via lldb-commits
https://github.com/DavidSpickett closed https://github.com/llvm/llvm-project/pull/130034 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

2025-03-06 Thread David Spickett via lldb-commits
@@ -195,8 +195,17 @@ def test_qRegisterInfo_contains_required_generics_debugserver(self): # Ensure we have a stack pointer register. self.assertIn("sp", generic_regs) -# Ensure we have a flags register. -self.assertIn("flags", generic_regs) +

[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

2025-03-06 Thread David Spickett via lldb-commits
@@ -1393,6 +1393,11 @@ def isLoongArchLSX(self): def isLoongArchLASX(self): return self.isLoongArch() and "lasx" in self.getCPUInfo() +def isRISCV(self): +"""Returns true if the architecture is RISCV64 or RISCV32.""" +arch = self.getArchitecture

[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

2025-03-06 Thread David Spickett via lldb-commits
@@ -195,8 +195,17 @@ def test_qRegisterInfo_contains_required_generics_debugserver(self): # Ensure we have a stack pointer register. self.assertIn("sp", generic_regs) -# Ensure we have a flags register. -self.assertIn("flags", generic_regs) +