This revision was automatically updated to reflect the committed changes.
Closed by commit rG768e59d959c7: [LLDB][RISCV] Add riscv register enums
(authored by Emmmer).
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DavidSpickett accepted this revision.
DavidSpickett added a comment.
This revision is now accepted and ready to land.
As I understand it, these registers are the same across riscv32 and riscv64. So
LGTM.
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rG LLVM Github Monorepo
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Emmmer created this revision.
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