[Lldb-commits] [clang] [libc] [libcxx] [lldb] [llvm] [doc] Add Discord invite link alongside channel links (PR #126352)

2025-02-08 Thread Philip Reames via lldb-commits
https://github.com/preames approved this pull request. LGTM w/requested change. Another option would be to expand a section on joining discord somewhere, and then scatter links to that in the docs instead of the invite link itself. https://github.com/llvm/llvm-project/pull/126352

[Lldb-commits] [clang] [libc] [libcxx] [lldb] [llvm] [doc] Add Discord invite link alongside channel links (PR #126352)

2025-02-08 Thread Philip Reames via lldb-commits
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/126352 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [clang] [libc] [libcxx] [lldb] [llvm] [doc] Add Discord invite link alongside channel links (PR #126352)

2025-02-08 Thread Philip Reames via lldb-commits
@@ -149,7 +149,7 @@ Open Clang Projects If you hit a bug with Clang, it is very useful for us if you reduce the code that demonstrates the problem down to something small. There are many ways to do this; ask on https://discourse.llvm.org/c/clang";>Discourse, -https://discord.co

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef VL) { return CommonAlignment; } +/// Check if \p Order represents reverse order. +static bool isReverseOrder(ArrayRef Order) { + unsigned Sz = Order.size(); + return !Order.empty() && all_of(enumerate(Or

[Lldb-commits] [openmp] [clang-tools-extra] [libcxx] [lld] [flang] [clang] [llvm] [lldb] [mlir] [libc] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[Lldb-commits] [libcxx] [flang] [mlir] [openmp] [llvm] [clang] [clang-tools-extra] [lldb] [lld] [libc] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
https://github.com/preames commented: These comments are trying to be helpful in pointing out bits which might be simplified or split off, but my track record with SLP reviews is not great. Feel free to ignore any or all of these. https://github.com/llvm/llvm-project/pull/80310

[Lldb-commits] [flang] [libcxx] [lldb] [lld] [mlir] [clang-tools-extra] [libc] [openmp] [llvm] [clang] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -30,7 +30,7 @@ define void @test() { ; CHECK-SLP-THRESHOLD: bb: ; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison, ptr [[COND_IN_V]], i32 0 ; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <4

[Lldb-commits] [clang] [libc] [lld] [llvm] [lldb] [libcxx] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -17,7 +17,7 @@ define i16 @test() { ; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison) ; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0 ; CHECK-NEXT:[[TMP6:%.*]] =

[Lldb-commits] [flang] [libc] [mlir] [libcxx] [lldb] [lld] [clang] [openmp] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr [[P:%.*]], i64 0, i64 0 ; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[

[Lldb-commits] [flang] [clang] [openmp] [mlir] [libc] [lldb] [lld] [clang-tools-extra] [llvm] [libcxx] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[Lldb-commits] [mlir] [clang] [libc] [lldb] [lld] [openmp] [flang] [libcxx] [clang-tools-extra] [llvm] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
https://github.com/preames edited https://github.com/llvm/llvm-project/pull/80310 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ADDR:%.*]], i32 0 ; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> ze

[Lldb-commits] [libcxx] [libc] [mlir] [clang-tools-extra] [openmp] [llvm] [lldb] [clang] [flang] [lld] [SLP]Add support for strided loads. (PR #80310)

2024-02-01 Thread Philip Reames via lldb-commits
preames wrote: FYI - https://github.com/llvm/llvm-project/pull/80360 adds testing infrastructure to exercise the TTI hooks. https://github.com/llvm/llvm-project/pull/80310 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.or

[Lldb-commits] [compiler-rt] [llvm] [clang-tools-extra] [lld] [clang] [libc] [libcxx] [lldb] [flang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +

[Lldb-commits] [clang-tools-extra] [clang] [libcxx] [compiler-rt] [lldb] [llvm] [flang] [lld] [libc] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +

[Lldb-commits] [lldb] [compiler-rt] [clang-tools-extra] [llvm] [flang] [clang] [libcxx] [libc] [lld] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

2024-02-01 Thread Philip Reames via lldb-commits
@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp)) { +unsigned TpRegs = getRegUsageForType(Tp); +unsigned NumElems = +