[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket

[Lldb-commits] [lldb] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/michaelmaitland review_requested https://github.com/llvm/llvm-project/pull/65535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits