[Lldb-commits] [clang] [lld] [libcxx] [clang-tools-extra] [lldb] [mlir] [openmp] [libc] [llvm] [flang] [SLP]Add support for strided loads. (PR #80310)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80310 >From 92950afd39034c0184a3c807f8062e0053eead5c Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 1 Feb 2024 17:22:34 + Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[Lldb-commits] [libcxxabi] [lldb] [clang] [flang] [compiler-rt] [lld] [libc] [clang-tools-extra] [libcxx] [llvm] [SLP]Improve findReusedOrderedScalars and graph rotation. (PR #77529)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/77529 >From 7440ee8ba235fd871af0999f66d5d6130456400b Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Jan 2024 21:43:31 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [lldb] [clang] [clang-tools-extra] [libcxxabi] [libc] [flang] [llvm] [lld] [libcxx] [compiler-rt] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

@@ -326,6 +326,48 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp) && + LT.second.getVectorElementType() != MVT::i1) { +unsigned TpReg

[Lldb-commits] [lldb] [clang] [clang-tools-extra] [libcxxabi] [libc] [flang] [llvm] [lld] [libcxx] [compiler-rt] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80164 >From cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 31 Jan 2024 16:47:49 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [lldb] [libcxx] [clang] [libc] [llvm] [libcxxabi] [flang] [lld] [compiler-rt] [clang-tools-extra] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

@@ -326,6 +326,48 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, switch (Kind) { default: break; +case TTI::SK_ExtractSubvector: + if (isa(SubTp) && + LT.second.getVectorElementType() != MVT::i1) { +unsigned TpReg

[Lldb-commits] [compiler-rt] [libc] [libcxx] [libcxxabi] [llvm] [clang-tools-extra] [lld] [lldb] [clang] [flang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80164 >From cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 31 Jan 2024 16:47:49 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80310 >From 92950afd39034c0184a3c807f8062e0053eead5c Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 1 Feb 2024 17:22:34 + Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -3930,30 +4065,68 @@ static LoadsState canVectorizeLoads(ArrayRef VL, const Value *VL0, std::optional Diff = getPointersDiff(ScalarTy, Ptr0, ScalarTy, PtrN, DL, SE); // Check that the sorted loads are consecutive. - if (static_cast(*Diff) == VL.si

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -3878,6 +3883,130 @@ static Align computeCommonAlignment(ArrayRef VL) { return CommonAlignment; } +/// Check if \p Order represents reverse order. +static bool isReverseOrder(ArrayRef Order) { + unsigned Sz = Order.size(); + return !Order.empty() && all_of(enumerate(Or

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -397,27 +241,12 @@ define void @test3([48 x float]* %p, float* noalias %s) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds [48 x float], ptr [[P:%.*]], i64 0, i64 0 ; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -7,7 +7,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) { ; CHECK-NEXT: entry: ; CHECK-NEXT:[[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ADDR:%.*]], i32 0 ; CHECK-NEXT:[[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> ze

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -30,7 +30,7 @@ define void @test() { ; CHECK-SLP-THRESHOLD: bb: ; CHECK-SLP-THRESHOLD-NEXT:[[TMP0:%.*]] = insertelement <4 x ptr> poison, ptr [[COND_IN_V]], i32 0 ; CHECK-SLP-THRESHOLD-NEXT:[[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <4

[Lldb-commits] [libcxx] [lldb] [clang] [lld] [libc] [llvm] [mlir] [flang] [openmp] [clang-tools-extra] [SLP]Add support for strided loads. (PR #80310)

@@ -17,7 +17,7 @@ define i16 @test() { ; CHECK-NEXT:[[TMP4:%.*]] = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> [[TMP3]], i32 2, <2 x i1> , <2 x i16> poison) ; CHECK-NEXT:[[TMP5:%.*]] = extractelement <2 x i16> [[TMP4]], i32 0 ; CHECK-NEXT:[[TMP6:%.*]] =

[Lldb-commits] [clang] [flang] [openmp] [libcxx] [clang-tools-extra] [mlir] [lldb] [llvm] [lld] [libc] [SLP]Add support for strided loads. (PR #80310)

https://github.com/alexey-bataev edited https://github.com/llvm/llvm-project/pull/80310 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [llvm] [libcxx] [libc] [clang-tools-extra] [mlir] [lld] [lldb] [openmp] [clang] [flang] [SLP]Add support for strided loads. (PR #80310)

https://github.com/alexey-bataev edited https://github.com/llvm/llvm-project/pull/80310 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [llvm] [libcxx] [libc] [clang-tools-extra] [mlir] [lld] [lldb] [openmp] [clang] [flang] [SLP][TTI]Add support for strided loads. (PR #80310)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80310 >From 92950afd39034c0184a3c807f8062e0053eead5c Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 1 Feb 2024 17:22:34 + Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[Lldb-commits] [clang-tools-extra] [libcxx] [lldb] [lld] [llvm] [compiler-rt] [libc] [libcxxabi] [flang] [clang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80164 >From cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 31 Jan 2024 16:47:49 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [lldb] [clang-tools-extra] [libcxx] [lld] [libcxxabi] [clang] [libc] [llvm] [compiler-rt] [flang] [SLP]Improve findReusedOrderedScalars and graph rotation. (PR #77529)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/77529 >From 7440ee8ba235fd871af0999f66d5d6130456400b Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Jan 2024 21:43:31 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [lld] [llvm] [libc] [lldb] [compiler-rt] [clang-tools-extra] [flang] [libcxx] [clang] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/80164 >From cfd0dcfa1f5fabd12cf4d7bf8d5a10bd324ace0a Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 31 Jan 2024 16:47:49 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [llvm] [clang-tools-extra] [flang] [libc] [mlir] [lldb] [libcxx] [compiler-rt] [clang] [OpenMP] atomic compare weak : Parser & AST support (PR #79475)

https://github.com/alexey-bataev closed https://github.com/llvm/llvm-project/pull/79475 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [clang] [llvm] [libc] [compiler-rt] [lld] [libcxx] [clang-tools-extra] [libcxxabi] [flang] [SLP]Improve findReusedOrderedScalars and graph rotation. (PR #77529)

https://github.com/alexey-bataev updated https://github.com/llvm/llvm-project/pull/77529 >From 7440ee8ba235fd871af0999f66d5d6130456400b Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Jan 2024 21:43:31 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=

[Lldb-commits] [clang] [flang] [mlir] [libc] [llvm] [clang-tools-extra] [compiler-rt] [lldb] [OpenMP] atomic compare weak : Parser & AST support (PR #79475)

https://github.com/alexey-bataev approved this pull request. LG https://github.com/llvm/llvm-project/pull/79475 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [libc] [clang-tools-extra] [openmp] [flang] [compiler-rt] [polly] [llvm] [libcxxabi] [mlir] [clang] [lldb] [libcxx] [OpenMP] Patch for Support to loop bind clause : Checking Parent Regi

https://github.com/alexey-bataev approved this pull request. LG https://github.com/llvm/llvm-project/pull/76938 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [libcxxabi] [libc] [flang] [llvm] [lldb] [mlir] [compiler-rt] [clang-tools-extra] [libcxx] [openmp] [clang] [OpenMP] Patch for Support to loop bind clause : Checking Parent Region (PR #

@@ -6124,35 +6136,39 @@ processImplicitMapsWithDefaultMappers(Sema &S, DSAStackTy *Stack, bool Sema::mapLoopConstruct(llvm::SmallVector &ClausesWithoutBind, ArrayRef Clauses, -OpenMPBindClauseKind BindKind, +

[Lldb-commits] [lldb] [llvm] [clang] [OpenACC] Implement initial parsing for `parallel` construct (PR #72661)

https://github.com/alexey-bataev approved this pull request. https://github.com/llvm/llvm-project/pull/72661 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [clang] [llvm] [OpenACC] Implement initial parsing for Construct/Directive Names (PR #72661)

@@ -0,0 +1,72 @@ +//===--- OpenACCKinds.h - OpenACC Enums -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [clang] [lldb] [llvm] [OpenACC] Implement initial parsing for Construct/Directive Names (PR #72661)

@@ -10,18 +10,240 @@ // //===--===// +#include "clang/Basic/OpenACCKinds.h" #include "clang/Parse/ParseDiagnostic.h" #include "clang/Parse/Parser.h" +#include "clang/Parse/RAIIObjectsForParser.h" +#include

[Lldb-commits] [llvm] [clang] [lldb] [OpenACC] Implement initial parsing for Construct/Directive Names (PR #72661)

@@ -10,18 +10,240 @@ // //===--===// +#include "clang/Basic/OpenACCKinds.h" #include "clang/Parse/ParseDiagnostic.h" #include "clang/Parse/Parser.h" +#include "clang/Parse/RAIIObjectsForParser.h" +#include

[Lldb-commits] [flang] [lld] [libcxx] [clang] [libc] [lldb] [llvm] [clang-tools-extra] [OpenACC] Initial commits to support OpenACC (PR #70234)

https://github.com/alexey-bataev approved this pull request. https://github.com/llvm/llvm-project/pull/70234 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [flang] [lld] [libcxx] [clang] [libc] [lldb] [llvm] [clang-tools-extra] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -3633,6 +3633,22 @@ static void RenderHLSLOptions(const ArgList &Args, ArgStringList &CmdArgs, CmdArgs.push_back("-finclude-default-header"); } +static void RenderOpenACCOptions(const Driver &D, const ArgList &Args, + ArgStringList &CmdA

[Lldb-commits] [flang] [llvm] [clang] [lld] [libcxx] [lldb] [clang-tools-extra] [libc] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -4001,6 +4008,14 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, (T.isNVPTX() || T.isAMDGCN()) && Args.hasArg(options::OPT_fopenmp_cuda_mode); + // OpenACC Configuration. + if (Args.hasArg(option

[Lldb-commits] [clang] [libc] [flang] [clang-tools-extra] [llvm] [libcxx] [lld] [lldb] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -1349,6 +1349,19 @@ def fno_hip_emit_relocatable : Flag<["-"], "fno-hip-emit-relocatable">, HelpText<"Do not override toolchain to compile HIP source to relocatable">; } +// Clang specific/exclusive options for OpenACC. +def openacc_macro_override alexey

[Lldb-commits] [flang] [llvm] [clang] [lld] [libcxx] [lldb] [clang-tools-extra] [libc] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -229,6 +230,9 @@ class Parser : public CodeCompletionHandler { /// Parsing OpenMP directive mode. bool OpenMPDirectiveParsing = false; + /// Parsing OpenACC directive mode. + bool OpenACCDirectiveParsing = false; alexey-bataev wrote: I think better t

[Lldb-commits] [flang] [llvm] [clang] [lld] [libcxx] [lldb] [clang-tools-extra] [libc] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -229,6 +230,9 @@ class Parser : public CodeCompletionHandler { /// Parsing OpenMP directive mode. bool OpenMPDirectiveParsing = false; + /// Parsing OpenACC directive mode. + bool OpenACCDirectiveParsing = false; alexey-bataev wrote: I mean, it has v

[Lldb-commits] [lldb] [clang] [libc] [llvm] [clang-tools-extra] [libcxx] [lld] [flang] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -0,0 +1,14 @@ +// RUN: %clang -S -### -fopenacc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DRIVER +// CHECK-DRIVER: "-cc1" {{.*}} "-fopenacc" + +// RUN: %clang -S -### -fopenacc -fexperimental-openacc-macro-override=202211 %s 2>&1 | FileCheck %s --check-prefix=CHECK-MACRO-OV

[Lldb-commits] [flang] [llvm] [lld] [libcxx] [lldb] [clang-tools-extra] [libc] [clang] [OpenACC] Initial commits to support OpenACC (PR #70234)

@@ -229,6 +230,9 @@ class Parser : public CodeCompletionHandler { /// Parsing OpenMP directive mode. bool OpenMPDirectiveParsing = false; + /// Parsing OpenACC directive mode. + bool OpenACCDirectiveParsing = false; alexey-bataev wrote: It is unused, ne