omjavaid added inline comments.
Comment at:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:222
+ // In SIMD or Full mode, the data comes from the SVE regset. In streaming
+ // mode, it also comes from that set, so we have to switch temporarily.
omjavaid added inline comments.
Comment at:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:325
+ } else if (IsSME(reg)) {
+// This is a pseduo so it never fails.
+ReadSMEControl();
typo: pseudo register?
Comme
omjavaid added inline comments.
Comment at:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:279
+assert(offset < GetTLSSize());
+src = (uint8_t *)GetTLS() + offset;
} else if (IsSVE(reg)) {
GetTLS could be GetTLSBuffer similar t
jasonmolenda added a comment.
Isn't it better to print branches within a function as an offset, given that
our disassembly format by default lists the offset of each instruction. So
instead of looking for a 6-digit long hex address, you're looking for a decimal
offset in the output? I'm not s
xgupta abandoned this revision.
xgupta added a comment.
I am sorry for taking time, but I could not understand the right issue. Hence I
am abandoning it.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D142341/new/
https://reviews.llvm.org/D142341
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