On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
> Dear all,
>
> I have a problem in MPC5121 sleep mode. As you know MPC5121 use e300c4
> core. When I make the e300c4 core into sleep mode, it will return to
> full power mode when the“decrementer interrupt” occurred.
>
> But in the e300 cor
On Wed, 2009-09-09 at 13:43 -0500, Scott Wood wrote:
> On Wed, Sep 09, 2009 at 01:16:07PM +0200, Kenneth Johansson wrote:
> > On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
> > > Dear all,
> > >
> > > I have a problem in MPC5121 sleep mode. As you know
On Mon, 2009-10-12 at 15:54 +0200, Fortini Matteo wrote:
> Yes, that's what we're currently using, but the problem is a little
> broader: I should answer to CAN messages in at most 100-200ms from
> powerup, and that can be done in u-boot.
if you are in that interval you definitely need to go to
On Mon, 2009-10-19 at 09:52 +0200, Fortini Matteo wrote:
> I didn't find a cleaner way than just #ifdef'ing the map_copy_from call
> and substitute with my call on relevant cases. I wonder if there is a
> cleaner way.
Remove the call to simple_map_init() and do it manually in your driver
with y
th the default block size (I believe it's 512Bytes), fetches from
> /dev/mtd0 4096 Bytes at a time.
> I'd prefer the kernel to be scheduling other tasks meanwhile, instead of
> busy-waiting on completion.
>
> Regards
>
> Kenneth Johansson ha scritto:
> >
On Tue, 2009-10-27 at 16:52 -0600, Jonathan Haws wrote:
> > Jonathan Haws wrote:
> > > I had thought about using MTD, but decided against it because with
> > > previous benchmarking that we did with MTD and our custom driver,
> > we
> > > found that our custom driver was about 10x faster.
> >
> >
On Thu, 2009-10-29 at 10:00 +0100, Joakim Tjernlund wrote:
> >
> > > > On Tue, Oct 27, 2009 at 04:24:53PM -0600, Jonathan Haws wrote:
> > > > >> >>> How can I get that pointer? Unfortunately I cannot simply
> > > > use
> > > > >> the
> > > > >> >>>
> > > > >> >> address of the flash. Is there som
a LRW table for chosing the TLB-way.
>
> Signed-off-by: Kumar Gala
> Signed-off-by: David Jander
I think we have a winner. with one instruction slot left :)
I tried your V4 and V5 and could not see any difference in speed.
Ack
http://www.cambridgewireless.co.uk/news/article/default.aspx?objid=36792
Anybody know what they mean by booting here.
I have started the ads5121 board using u-boot and kernel in NOR flash
and root file system on a compact flash card connected to the IDE
interface in 2.05 second until init is sta
On Wed, 2009-06-03 at 08:51 +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2009-06-02 at 20:45 +0200, Albrecht Dreß wrote:
>
> >
> > which drops the r1 accesses, but still produces the sub-optimal loop.
> > Is this a gcc regression, or did I miss something here? Probably the
> > only bullet
I have a bit of a problem with arch/powerpc/platforms/512x/mpc512x_pm.c
Since this one is not included in mainline (yet) I have attached it
Now I have a number of questions and one mystery.
1: why relocate the code ?? is there a reason why the code must be
located at address 0
http://www.bitsh
On Wed, 2009-08-05 at 01:06 +0200, Sebastian Andrzej Siewior wrote:
> I've tried kexec on e300 core which should be easy since it is possible
> to disable the MMU on that core. However it does not work.
Is it not possible to disable the mmu on all cpu's that have one ??
> Once I disable the MMU,
On Wed, 2009-08-05 at 18:47 -0500, Scott Wood wrote:
> On Thu, Aug 06, 2009 at 12:49:45AM +0200, Kenneth Johansson wrote:
> > On Wed, 2009-08-05 at 01:06 +0200, Sebastian Andrzej Siewior wrote:
> > > I've tried kexec on e300 core which should be easy since it is possible
&
on 5121 there is a e300 core that unfortunately is connected to the rest
of the SOC with a bus that do not support coherency.
solution for many driver has been to use uncached memory. But for the
framebuffer that is not going to work as the performance impact of doing
graphics operations on uncach
On Fri, 2009-08-07 at 14:56 -0500, Scott Wood wrote:
> On Fri, Aug 07, 2009 at 02:53:52PM +0200, Kenneth Johansson wrote:
> > on 5121 there is a e300 core that unfortunately is connected to the rest
> > of the SOC with a bus that do not support coherency.
> >
> > soluti
On Mon, 2009-08-10 at 15:26 -0500, Scott Wood wrote:
> Kenneth Johansson wrote:
> >>> should not the framebuffer be marked as cache write through. that is the
> >>> W bit should be set in the tlb mapping. Why is this not done ? is that
> >>> feature also
I have tried to speed up u-boot by turning on I/D cache during boot.
It sort of works and gives quite a boost but I'm having problems with
the ethernet driver that no longer works.
What I'm seeing is that the cpu do not notice the ethernet hardwares
updates that is located in DRAM. Basically w
hing I found. Is this a design decision or an errata
for the current version of the chip ?
> On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <[EMAIL PROTECTED]> wrote:
> > I have tried to speed up u-boot by turning on I/D cache during boot.
> >
> > It sort of work
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