New bindings use "fsl,t1040-ucc-uart" as the compatible for qe-uart.
So add it.
Signed-off-by: Zhao Qiang
---
drivers/tty/serial/ucc_uart.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 1a7dc3c..481eb29 10
cpm_qe is supported on both powerpc and arm.
and the QE code has been moved from arch/powerpc into
drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl
to soc/fsl
Signed-off-by: Zhao Qiang
Acked-by: Rob Herring
---
Changes for v3
- NA
Changes for v4
- NA
Changes for v5
add qe node to t104xqds.dtsi
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
Changes for v4
- rebase
Changes for v5
- rebase
arch/powerpc/boot/dts/fsl/t104xqds.dtsi | 38 +
1 file changed, 38
Add IC, SI and SIRAM document of QE to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
Signed-off-by: Zhao Qiang
Acked-by: Rob Herring
---
changes for v2
- Add interrupt-controller in Required properties
- delete address-cells and size-cells for qe-si and qe-siram
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
index 830ea48..be7bab6 100644
--- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
+++ b/arch
qe_ic was put in drivers/soc/fsl/qe, but it should be in
drivers/irqchip.
Signed-off-by: Zhao Qiang
---
drivers/irqchip/Makefile| 1 +
drivers/{soc/fsl/qe => irqchip}/qe_ic.c | 0
drivers/{soc/fsl/qe => irqchip}/qe_ic.h | 0
drivers/soc/fsl/qe/Makefile | 2
Rx_sync and tx_sync are used by QE-TDM mode,
add them to struct ucc_fast_info.
Signed-off-by: Zhao Qiang
---
drivers/soc/fsl/qe/qe.c | 6 ++
include/soc/fsl/qe/qe.h | 2 ++
include/soc/fsl/qe/ucc_fast.h | 2 ++
3 files changed, 10 insertions(+)
diff --git a/drivers/soc/fsl/qe
Add tdm clock configuration in both qe clock system and ucc
fast controller.
Signed-off-by: Zhao Qiang
---
drivers/soc/fsl/qe/ucc.c | 450 ++
drivers/soc/fsl/qe/ucc_fast.c | 36
include/soc/fsl/qe/qe.h | 16 ++
include/soc/fsl/qe/ucc.h
Signed-off-by: Zhao Qiang
---
include/soc/fsl/qe/ucc_fast.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h
index b2633b7..e898895 100644
--- a/include/soc/fsl/qe/ucc_fast.h
+++ b/include/soc/fsl/qe/ucc_fast.h
QE has module to support TDM, some other protocols
supported by QE are based on TDM.
add a qe-tdm lib, this lib provides functions to the protocols
using TDM to configurate QE-TDM.
Signed-off-by: Zhao Qiang
---
drivers/soc/fsl/qe/Kconfig| 4 +
drivers/soc/fsl/qe/Makefile | 1
The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.
Signed-off-by: Zhao Qiang
---
MAINTAINERS|6 +
drivers/net/wan/Kconfig| 12 +
drivers/net/wan/Makefile |1 +
drivers/net/wan/fsl_ucc_hdlc.c | 1339
DS26522 is used for tdm, configured by SPI bus.
Add nodes under spi node to t104xd4rdb.dtsi.
Signed-off-by: Zhao Qiang
---
Documentation/devicetree/bindings/net/maxim,ds26522.txt | 13 +
arch/powerpc/boot/dts/t104xd4rdb.dtsi | 10 ++
2 files changed, 23
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
muram is used for qe, add qe_muram_ functions to manage
muram.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- no changes
Changes for v3:
- no changes
Changes for v4:
- no changes
Changes for v5:
- no changes
Changes for v5:
- using genalloc instead rheap
On 08/25/2015 07:11 AM, Laura Abbott wrote:
> -Original Message-
> From: Laura Abbott [mailto:labb...@redhat.com]
> Sent: Tuesday, August 25, 2015 7:11 AM
> To: Zhao Qiang-B45475; Wood Scott-B07421
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau
> -Original Message-
> From: Laura Abbott [mailto:labb...@redhat.com]
> Sent: Tuesday, August 25, 2015 7:32 AM
> To: Zhao Qiang-B45475; Wood Scott-B07421
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie Xiaobo-R63061; b...@k
On 08/25/2015 12:15 PM, Laura Abbott wrote
> -Original Message-
> From: Laura Abbott [mailto:labb...@redhat.com]
> Sent: Tuesday, August 25, 2015 12:15 PM
> To: Zhao Qiang-B45475; Wood Scott-B07421
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau
On Tue, 2015-08-25 at 12:35 +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, August 25, 2015 12:35 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On 08/25/2015 12:01 PM, Laura Abbott wrote:
> -Original Message-
> From: Laura Abbott [mailto:labb...@redhat.com]
> Sent: Tuesday, August 25, 2015 12:01 PM
> To: Zhao Qiang-B45475; Wood Scott-B07421
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, August 26, 2015 12:23 AM
> To: Zhao Qiang-B45475
> Cc: Laura Abbott; linux-ker...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; lau...@codeaurora.org; Xie Xiaobo-R63061;
> b...@kernel.crashing.or
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
muram is used for qe, add qe_muram_ functions to manage
muram.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- no changes
Changes for v3:
- no changes
Changes for v4:
- no changes
Changes for v5:
- no changes
Changes for v6:
- using genalloc instead rheap
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
hanges for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers/soc
On Wed, 2015-09-02 at 08:38AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 8:30 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Wed, 2015-09-02 at 10:18AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 10:18 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Wed, 2015-09-02 at 10:31AM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 10:31 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Wed, 2015-09-02 at 8:34AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 8:34 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Wed, 2015-09-02 at 10:33AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 10:33 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Wed, 2015-09-02 at 10:33AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 11:09 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Wed, 2015-09-02 at 10:18AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 10:18 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Mon, 2015-09-2 at 8:34 +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 02, 2015 8:34 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
Add new algo for genalloc, it finds the first available region
from a specific offset address of memory matching the size
requirement (no alignment constraint)
Signed-off-by: Zhao Qiang
---
include/linux/genalloc.h | 11 +++
lib/genalloc.c | 26 ++
2
muram is used for qe, add qe_muram_ functions to manage
muram.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- no changes
Changes for v3:
- no changes
Changes for v4:
- no changes
Changes for v5:
- no changes
Changes for v6:
- using genalloc instead rheap
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
hanges for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers/soc
On Wed, 2015-09-10 at 12:38AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, September 10, 2015 12:38 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Mon, 2015-09-10 at 12:39 -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, September 10, 2015 12:39 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Mon, 2015-09-11 at 06:09 -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 11, 2015 6:09 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Fri, 2015-09-11 at 06:07AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 11, 2015 6:07 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Fri, 2015-09-11 at 10:15AM -0500, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 11, 2015 10:15 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
Add new algo for genalloc, it reserve a specific region of
memory matching the size requirement (no alignment constraint)
Signed-off-by: Zhao Qiang
---
Changes for v9:
- reserve a specific region, if the return region
- is not during the specific region, return fail.
include
muram is used for qe, add qe_muram_ functions to manage
muram.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- no changes
Changes for v3:
- no changes
Changes for v4:
- no changes
Changes for v5:
- no changes
Changes for v6:
- using genalloc instead rheap
CPM and QE have the same muram, shared the same
muram management functions. Delete cpm_muram_* functions,
using qe_muram_*.
Signed-off-by: Zhao Qiang
---
Changes for v9:
- splitted from patch 3/5, modify cpm muram management functions.
arch/powerpc/include/asm/cpm.h | 59
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
On Mon, 2015-09-18 at 04:28 +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 4:28 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
Add new algo for genalloc, it reserve a specific region of
memory matching the size requirement (no alignment constraint)
Signed-off-by: Zhao Qiang
---
Changes for v9:
- reserve a specific region, if the return region
- is not during the specific region, return fail.
Changes for
Use genalloc to manage CPM/QE muram instead of rheap.
Signed-off-by: Zhao Qiang
---
Changes for v9:
- splitted from patch 3/5, modify cpm muram management functions.
Changes for v10:
- modify cpm muram first, then move to qe_common
- modify commit.
arch/powerpc
QE and CPM have the same muram, they use the same management
functions. Now QE support both ARM and PowerPC, it is necessary
to move QE to "driver/soc", so move the muram management functions
from cpm_common to qe_common for preparing to move QE code to "driver/soc"
Signe
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
On Tue, Sep 22, 2015 at 06:54AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 6:54 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Tue, Sep 22, 2015 at 10:26AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 10:26 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Tue, Sep 22, 2015 at 11:08AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 11:08 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 11:25 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie Xiaobo-R63061; b...@kernel.crashing.org; Li
>
On Tue, Sep 22, 2015 at 06:47 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 6:47 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Tue, Sep 22, 2015 at 06:56 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 22, 2015 6:56 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Wen, Sep 23, 2015 at 12:40 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 23, 2015 12:40 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeauro
On Wen, Sep 23, 2015 at 8:19 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 23, 2015 8:19 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeauro
On Wen, Sep 23, 2015 at 12:03 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 23, 2015 12:03 PM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeauro
On Fri, Sep 25, 2015 at 7:30 AM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 25, 2015 7:30 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xi
On Fri, Sep 25, 2015 at 1:08 PM +0800, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 25, 2015 1:08 PM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
Add new algo for genalloc, it reserve a specific region of
memory matching the size requirement (no alignment constraint)
Signed-off-by: Zhao Qiang
---
Changes for v9:
- reserve a specific region, if the return region
- is not during the specific region, return fail.
Changes for
Use genalloc to manage CPM/QE muram instead of rheap.
Signed-off-by: Zhao Qiang
---
Changes for v9:
- splitted from patch 3/5, modify cpm muram management functions.
Changes for v10:
- modify cpm muram first, then move to qe_common
- modify commit.
Changes for v11
QE and CPM have the same muram, they use the same management
functions. Now QE support both ARM and PowerPC, it is necessary
to move QE to "driver/soc", so move the muram management functions
from cpm_common to qe_common for preparing to move QE code to "driver/soc"
Signe
Use subsys_initcall to init qe to adapt ARM architecture.
Remove qe_reset from PowerPC platform file.
Signed-off-by: Zhao Qiang
---
arch/powerpc/platforms/83xx/km83xx.c | 2 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 --
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 --
arch
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
---
Changes for v6:
- patches set v6 include a new
Add new algo for genalloc, it reserve a specific region of
memory matching the size requirement (no alignment constraint)
Signed-off-by: Zhao Qiang
---
Changes for v9:
- reserve a specific region, if the return region
- is not during the specific region, return fail.
Changes for
Use genalloc to manage CPM/QE muram instead of rheap.
Signed-off-by: Zhao Qiang
---
Changes for v9:
- splitted from patch 3/5, modify cpm muram management functions.
Changes for v10:
- modify cpm muram first, then move to qe_common
- modify commit.
Changes for v11
QE and CPM have the same muram, they use the same management
functions. Now QE support both ARM and PowerPC, it is necessary
to move QE to "driver/soc", so move the muram management functions
from cpm_common to qe_common for preparing to move QE code to "driver/soc"
Signe
Use subsys_initcall to init qe to adapt ARM architecture.
Remove qe_reset from PowerPC platform file.
Signed-off-by: Zhao Qiang
---
Changes for v12:
- Nil
arch/powerpc/platforms/83xx/km83xx.c | 2 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 --
arch/powerpc/platforms/83xx
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
On Fri, 2015-10-23 at 11:10 AM, Wood Scott-B07421
wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, October 23, 2015 11:10 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Fri, Oct 23, 2015 at 11:20 AM, Wood Scott-B07421
wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, October 23, 2015 11:20 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Fri, 2015-10-23 at 11:00 AM, Wood Scott-B07421
wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, October 23, 2015 11:00 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org;
On Sat, Oct 24, 2015 at 04:56 AM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, October 24, 2015 4:56 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Sat, Oct 24, 2015 at 04:56 AM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, October 24, 2015 4:56 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Sat, 2015-10-24 at 04:59 AM, Wood Scott-B07421
wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, October 24, 2015 4:59 AM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Tue, Oct 27, 2015 at 12:48 PM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, October 27, 2015 12:48 PM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
On Tue, Oct 27, 2015 at 2:50 PM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, October 27, 2015 2:50 PM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie X
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_algo to pass algo in case user
layer using more than one algo, and pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
Add new algo for genalloc, it reserve a specific region of
memory
Signed-off-by: Zhao Qiang
---
Changes for v9:
- reserve a specific region, if the return region
- is not during the specific region, return fail.
Changes for v10:
- rename gen_pool_fixed_fit to
Use genalloc to manage CPM/QE muram instead of rheap.
Signed-off-by: Zhao Qiang
---
Changes for v9:
- splitted from patch 3/5, modify cpm muram management functions.
Changes for v10:
- modify cpm muram first, then move to qe_common
- modify commit.
Changes for v11
QE and CPM have the same muram, they use the same management
functions. Now QE support both ARM and PowerPC, it is necessary
to move QE to "driver/soc", so move the muram management functions
from cpm_common to qe_common for preparing to move QE code to "driver/soc"
Signe
Use subsys_initcall to init qe to adapt ARM architecture.
Remove qe_reset from PowerPC platform file.
Signed-off-by: Zhao Qiang
---
Changes for v12:
- Nil
Changes for v13:
- drop a print
arch/powerpc/platforms/83xx/km83xx.c | 2 --
arch/powerpc/platforms/83xx
ls1 has qe and ls1 has arm cpu.
move qe from arch/powerpc to drivers/soc/fsl
to adapt to powerpc and arm
Signed-off-by: Zhao Qiang
---
Changes for v2:
- move code to driver/soc
Changes for v3:
- change drivers/soc/qe to drivers/soc/fsl-qe
Changes for v4:
- move drivers
p1010rdb use the irq[4:5] for inta and intb to pcie,
it is active-high, so set it.
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/p1010rdb.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/p1010rdb.dtsi
b/arch/powerpc/boot/dts/fsl
add qe node to t104xqds.dtsi
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t104xqds.dtsi | 44 +
1 file changed, 44 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
b/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
index 1498d1e..8ebd574
Add IC, SI and SIRAM document of QE to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
Signed-off-by: Zhao Qiang
---
.../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt | 53 ++
1 file changed, 53 insertions(+)
diff --git a/Documentation/devicetree/bindings
add qe node to t104xrdb.dtsi
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 44 +
1 file changed, 44 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
index 830ea48..63649fa
Add maxim ds26522 document to
Documentation/devicetree/bindings/tdm/maxim,ds26522.txt
Signed-off-by: Zhao Qiang
---
Documentation/devicetree/bindings/tdm/maxim,ds26522.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/tdm/maxim
add tdm riser card node to t1040rdb.dts
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index cf19415..d52b011 100644
--- a/arch
add tdm riser card node to t1040d4rdb.dts
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t1040d4rdb.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
b/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
index fb6bc02..ee3d1ec
Add ucc hdlc document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
Signed-off-by: Zhao Qiang
---
.../bindings/powerpc/fsl/cpm_qe/network.txt| 35 ++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl
add qe node to t104xd4rdb.dtsi and t1040si-post.dtsi.
Signed-off-by: Zhao Qiang
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 45 +
arch/powerpc/boot/dts/fsl/t104xd4rdb.dtsi | 44
2 files changed, 89 insertions(+)
diff --git a/arch
Add uqe_serial document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
Signed-off-by: Zhao Qiang
---
.../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Documentation/devicetree/bindings
127 is the theoretical up boundary of QEIC number,
in fact there only be 44 qe_ic_info now.
add check to overflow for qe_ic_info
Signed-off-by: Zhao Qiang
---
drivers/soc/fsl/qe/qe_ic.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b
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