The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/x86/net/bpf_jit_comp32
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/riscv/net
p me test this. Especially,
the powerpc32 JTI where amount of code change is more.
[1]
https://lore.kernel.org/all/CANk7y0j2f-gPgZwd+YfTL71-6wfvky+f=kbc_ccqss0ehay...@mail.gmail.com/
Puranjay Mohan (6):
bpf, riscv32: Always zero extend for LDX with B/W/H
bpf, x86-32: Always zero extend for LDX wit
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/parisc/net
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/powerpc/net
zero extend the
destination.
Now the verifier can safely mark LDX destination as 64-bit and stop
emitting zero-extension instructions for it.
Signed-off-by: Puranjay Mohan
---
kernel/bpf/verifier.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/kernel/bpf/verifier.c b/kernel
The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.
A following patch will make the verifier stop patching zext instructions
after LDX.
Signed-off-by: Puranjay Mohan
---
arch/arm/net/bpf_jit_32.c
On Wed, Sep 13, 2023 at 1:04 AM Russell King (Oracle)
wrote:
>
> On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> > The JITs should not depend on the verifier for zero extending the upper
> > 32 bits of the destination register when loading a byte, half
y be different :)
> >
> > What I mean is that jit_alloc_arch_params() tries to aggregate common
> > parameters, but they aren't actually common (e.g. the actual start+end range
> > for allocation).
> >
> > > Can you give more detail on what parameters you
On Mon, Jun 26, 2023 at 8:13 AM Song Liu wrote:
>
> On Sun, Jun 25, 2023 at 11:07 AM Kent Overstreet
> wrote:
> >
> > On Sun, Jun 25, 2023 at 08:42:57PM +0300, Mike Rapoport wrote:
> > > On Sun, Jun 25, 2023 at 09:59:34AM -0700, Andy Lutomirski wrote:
> > > >
> > > >
> > > > On Sun, Jun 25, 2023,
)
Observation SB+atomic_add+fetch Never 0 9
[1] https://www.kernel.org/doc/Documentation/memory-barriers.txt
[2] https://www.kernel.org/doc/Documentation/atomic_t.txt
Fixes: 65112709115f ("powerpc/bpf/64: add support for BPF_ATOMIC bitwise
operations")
Signed-off-by: Puranjay Mohan
---
arch/p
Michael Ellerman writes:
> Puranjay Mohan writes:
>> The Linux Kernel Memory Model [1][2] requires RMW operations that have a
>> return value to be fully ordered.
>>
>> BPF atomic operations with BPF_FETCH (including BPF_XCHG and
>> BPF_CMPXCHG) return a value
)
Observation SB+atomic_add+fetch Never 0 9
[1] https://www.kernel.org/doc/Documentation/memory-barriers.txt
[2] https://www.kernel.org/doc/Documentation/atomic_t.txt
Fixes: 65112709115f ("powerpc/bpf/64: add support for BPF_ATOMIC bitwise
operations")
Signed-off-by: Puranjay Mohan
---
Changes i
)
Observation SB+atomic_add+fetch Never 0 9
[1] https://www.kernel.org/doc/Documentation/memory-barriers.txt
[2] https://www.kernel.org/doc/Documentation/atomic_t.txt
Fixes: 65112709115f ("powerpc/bpf/64: add support for BPF_ATOMIC bitwise
operations")
Signed-off-by: Puranjay Mohan
Acked-
Naveen N Rao writes:
> On Mon, May 13, 2024 at 10:02:48AM GMT, Puranjay Mohan wrote:
>> The Linux Kernel Memory Model [1][2] requires RMW operations that have a
>> return value to be fully ordered.
>>
>> BPF atomic operations with BPF_FETCH (including BPF_XCHG and
>
lease to pkt pointer:OK
#556/26 verifier_store_release/store-release to flow_keys pointer:OK
#556/27 verifier_store_release/store-release to sock pointer:OK
#556 verifier_store_release:OK
Summary: 3/55 PASSED, 0 SKIPPED, 0 FAILED
Signed-off-by: Puranjay Mohan
---
arch/powerpc/include/asm/
lease to pkt pointer:OK
#556/26 verifier_store_release/store-release to flow_keys pointer:OK
#556/27 verifier_store_release/store-release to sock pointer:OK
#556 verifier_store_release:OK
Summary: 3/55 PASSED, 0 SKIPPED, 0 FAILED
Signed-off-by: Puranjay Mohan
---
arch/powerpc/include/asm/
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