On Wed, Feb 17, 2016 at 10:09 PM, Michael Ellerman
wrote:
> On Wed, 2016-02-17 at 16:07 +1100, Michael Neuling wrote:
>
> > Add a cputable entry for POWER9. More code is required to actually
> > boot and run on a POWER9 but this gets the base piece in which we can
> > start building on.
> >
> >
of the switch and letting it
propagate should be the right move here.
Oliver
On Wed, Jan 27, 2016 at 11:52 AM, Andrew Donnellan <
andrew.donnel...@au1.ibm.com> wrote:
> On 25/01/16 17:55, Oliver O'Halloran wrote:
>
>> I think this bug can only be triggered if the in
On Thu, Feb 28, 2019 at 7:35 PM Aneesh Kumar K.V
wrote:
>
> Add a flag to indicate the ability to do huge page dax mapping. On
> architecture
> like ppc64, the hypervisor can disable huge page support in the guest. In
> such a case, we should not enable huge page dax mapping. This patch adds
> a
On Sat, Mar 2, 2019 at 3:04 AM Sergey Miroshnichenko
wrote:
>
> This patchset allows switching from the pnv_php module to the standard
> pciehp driver for PCIe hotplug functionality, if the platform supports it:
> PowerNV working on on top of the skiboot with the "core/pci: Sync VFs and
> the chan
On Sat, Mar 2, 2019 at 3:04 AM Sergey Miroshnichenko
wrote:
>
> Reading an empty slot returns all ones, which triggers a false
> EEH error event on PowerNV. This patch unfreezes the bus where
> it has happened.
>
> Signed-off-by: Sergey Miroshnichenko
> ---
> arch/powerpc/include/asm/ppc-pci.h
On Sat, Mar 2, 2019 at 3:04 AM Sergey Miroshnichenko
wrote:
>
> If a struct pci_dn hasn't yet been created for the PCIe device (there was
> no DT node for it), allocate this structure and fill with info read from
> the device directly.
>
> Signed-off-by: Sergey Miroshnichenko
> ---
> arch/powerp
On Wed, Mar 20, 2019 at 5:06 PM Alexey Kardashevskiy wrote:
>
>
>
> On 20/03/2019 13:58, Sam Bobroff wrote:
> > Move the EEH enabled message into it's own function so that future
> > work can call it from multiple places.
> >
> > Signed-off-by: Sam Bobroff
> > ---
> > arch/powerpc/include/asm/ee
On Thu, Mar 21, 2019 at 7:57 AM Dan Williams wrote:
>
> On Wed, Mar 20, 2019 at 8:34 AM Dan Williams wrote:
> >
> > On Wed, Mar 20, 2019 at 1:09 AM Aneesh Kumar K.V
> > wrote:
> > >
> > > Aneesh Kumar K.V writes:
> > >
> > > > Dan Williams writes:
> > > >
> > > >>
> > > >>> Now what will be pa
On Thu, Mar 28, 2019 at 1:10 AM Bjorn Helgaas wrote:
>
> Hi Sergey,
>
> Since this doesn't touch drivers/pci, I assume powerpc folks will
> handle this series. Let me know if otherwise.
I've been looking at it and reviewed the last spin. I'll have another
look next week.
> On Mon, Mar 11, 2019
On Fri, Mar 15, 2019 at 11:55 AM Jordan Niethe wrote:
>
> The sysfs nodes created under /opal/exports/ do not currently support
> mmap. Skiboot trace buffers are not yet added to this location but
> this is a suitable for them to be exported to. Adding mmap support makes
> using these trace buffer
On Mon, Apr 8, 2019 at 1:06 PM Christopher M. Riedl wrote:
>
> Operations which write to memory and special purpose registers should be
> restricted on systems with integrity guarantees (such as Secure Boot)
> and, optionally, to avoid self-destructive behaviors.
>
> Add a config option, XMON_RW,
On Wed, Apr 10, 2019 at 12:35 PM Christopher M Riedl
wrote:
>
>
> > On April 8, 2019 at 1:34 AM Oliver wrote:
> >
> >
> > On Mon, Apr 8, 2019 at 1:06 PM Christopher M. Riedl
> > wrote:
> > >
> > > Operations which write to memory and s
e memory" for itself) and expect things to work.
Good cleanup. ARCH_HAS_ZONE_DEVICE made sense at the time, but it
probably should have been renamed after the memory hotplug rework.
+cc mpe since he does the merging, and
Acked-by: Oliver O'Halloran
> In practice, however, ZONE_D
mex:
> no-op'd mwrite
> super_regs:
> no-op'd write_spr
> bpt_cmds:
> disable
> proc_call:
> disable
>
> Signed-off-by: Christopher M. Riedl
Reviewed-by: Oliver O'Halloran
> ---
>
> v2->v3:
>
On Tue, Sep 11, 2018 at 9:56 PM, Sergey Miroshnichenko
wrote:
> This patchset allows hotplugged PCIe devices to be enumerated during a bus
> rescan being issued via sysfs on PowerNV platforms, when the "Presence
> Detect Changed" interrupt is not available.
Seems to be on par with the sysfs slot
gt;> > generic PCI error handling strategy.
>>
>> I really want to make sure the powerpc folks are plugged into any PCI core
>> error handling discussions. Please let me know if there's a better way
>> than this patch, or if there are other people who should be added
On Wed, Sep 19, 2018 at 3:52 PM, Christophe LEROY
wrote:
>
>
> Le 19/09/2018 à 01:07, Joel Stanley a écrit :
>>
>> This partially reverts faa16bc404d72a5 ("lib: Use existing define with
>> polynomial").
>>
>> The cleanup added a dependency on include/linux, which broke the PowerPC
>> boot wrapper/
On Mon, Sep 24, 2018 at 6:56 PM, Abdul Haleem
wrote:
> Greeting's
>
> bnx2x module load/unload test results in continuous hard LOCKUP trace on
> my powerpc bare-metal running mainline 4.19.0-rc4 kernel
>
> the instruction address points to:
>
> 0xc009d048 is in opal_interrupt
> (arch/power
On Thu, Oct 11, 2018 at 3:36 AM Nathan Fontenot
wrote:
>
> On 10/10/2018 01:08 AM, Oliver O'Halloran wrote:
> > This patch implements support for discovering storage class memory
> > devices at boot and for handling hotplug of new regions via RTAS
> > hotplug events.
On Sat, Oct 13, 2018 at 9:37 AM Dan Williams wrote:
>
> On Tue, Oct 9, 2018 at 11:21 PM Oliver O'Halloran wrote:
> >
> > Adds a driver that implements support for enabling and accessing PAPR
> > SCM regions. Unfortunately due to how the PAPR interface works we can&#
On Mon, Oct 15, 2018 at 10:44 AM Dan Williams wrote:
>
> On Sun, Oct 14, 2018 at 4:19 PM Oliver O'Halloran wrote:
> >
> > Adds a driver that implements support for enabling and accessing PAPR
> > SCM regions. Unfortunately due to how the PAPR interface works we can&#
On Tue, Oct 30, 2018 at 1:28 AM Koltsov Dmitriy wrote:
>
> Hello.
>
> There is an EEH/NVMe-issue on SUT ppc64le POWER8-based server Yadro VESNIN
> (with minimum 2 NVMe disks) with
> Linux OS kernel 4.15.17/4.15.18/4.16.7 (OS - Ubuntu 16.04.5 LTS(hwe)/18.04.1
> LTS or Fedora 27).
>
> The issue is
On Fri, Nov 9, 2018 at 2:30 AM Koltsov Dmitriy wrote:
>
> Hi, Oliver.
>
> Your version of EEH/NVMe-issue looks close to be true.
>
> I've applied simple patch to ./drivers/nvme/host/pci.c file:
>
> @@ -29,6 +29,7 @@
> #include
> #include
> #inclu
On Tue, Dec 11, 2018 at 8:52 AM Arnd Bergmann wrote:
>
> For this use case, completions and semaphores are equivalent,
> but semaphores are an awkward interface that should generally
> be avoided, so use the completion instead.
IIRC Sam has been reworking the locking used inside of EEH so this is
On Wed, Jan 9, 2019 at 9:31 AM Bjorn Helgaas wrote:
>
> Hi,
>
> I want to update the PCI Kconfig labels so they're more consistent and
> useful to users, something like the patch below. IIUC, the items
> below are all IBM-related; please correct me if not.
>
> I'd also like to expand (or remove)
On Mon, Feb 4, 2019 at 3:45 PM Alexey Kardashevskiy wrote:
>
>
>
> On 01/02/2019 11:42, Oliver O'Halloran wrote:
> > The IODA reset is used to flush out any OS controlled state from the PHB.
> > This reset can fail if a PHB fatal error has occurred in early boot,
>
On Fri, Feb 8, 2019 at 11:32 PM Michael Ellerman wrote:
>
> Oliver O'Halloran writes:
>
> > This patch adds a debugfs interface to force scheduling a recovery event.
> > This can be used to recover a specific PE or schedule a "special" recovery
> > ev
On Fri, Feb 8, 2019 at 8:58 PM Michael Ellerman wrote:
>
> Oliver O'Halloran writes:
>
> > diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
> > index d1f0bdf41fac..92809b137e39 100644
> > --- a/arch/powerpc/kernel/eeh.c
> > +++ b/ar
On Fri, Feb 8, 2019 at 8:57 PM Michael Ellerman wrote:
>
> Oliver O'Halloran writes:
> > diff --git a/arch/powerpc/include/asm/pci-bridge.h
> > b/arch/powerpc/include/asm/pci-bridge.h
> > index aee4fcc24990..149053b7f481 100644
> > --- a/arch/powerpc/incl
On Fri, Feb 8, 2019 at 8:47 PM Michael Ellerman wrote:
>
> Oliver O'Halloran writes:
> > diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
> > index f6e65375a8de..d1f0bdf41fac 100644
> > --- a/arch/powerpc/kernel/eeh.c
> > +++ b/arch/powerpc/
On Wed, Feb 13, 2019 at 3:38 PM Sam Bobroff wrote:
>
> On Fri, Feb 08, 2019 at 02:08:02PM +1100, Oliver O'Halloran wrote:
> > This patch adds a debugfs interface to force scheduling a recovery event.
> > This can be used to recover a specific PE or schedule a "spe
canning
> (where this is already the case) and at boot time, which should
> support improvements and refactoring.
>
> Signed-off-by: Sam Bobroff
Reviewed-by: Oliver O'Halloran
> ---
> Hi everyone,
>
> I've tested this on a P9 for both the host and a KVM guest, and
On Fri, Feb 15, 2019 at 4:58 PM Sam Bobroff wrote:
>
> On Fri, Feb 15, 2019 at 11:48:16AM +1100, Oliver O'Halloran wrote:
> > Currently when we detect an error we automatically invoke the EEH recovery
> > handler. This can be annoying when debugging EEH problems, or when wo
On Fri, Feb 22, 2019 at 2:24 PM Sam Bobroff wrote:
>
> Hey all,
>
> After some consideration, I've decided to post a v2 of this patch that
> will make it a bit safer (although I haven't seen any problems with it)
> and make it a little easier to refactor some of the EEH code that
> interacts with
On Mon, Jun 4, 2018 at 12:44 PM, Haren Myneni wrote:
> On 06/03/2018 05:41 PM, Stewart Smith wrote:
>> Haren Myneni writes:
>>> On 06/01/2018 12:41 AM, Stewart Smith wrote:
Haren Myneni writes:
> NX increments readOffset by FIFO size in receive FIFO control register
> when CRB is re
ontroller *hose = pci_bus_to_host(bus);
> + struct pnv_phb *phb = hose->private_data;
> int ret;
>
> *val = 0x;
> pdn = pci_get_pdn_by_devfn(bus, devfn);
> if (!pdn)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> + return pnv_pci_cfg_read_raw(phb->opal_id, bus->number, devfn,
> + where, size, val);
>
> if (!pnv_pci_cfg_check(pdn))
> return PCIBIOS_DEVICE_NOT_FOUND;
> @@ -777,12 +797,14 @@ static int pnv_pci_write_config(struct pci_bus *bus,
> int where, int size, u32 val)
> {
> struct pci_dn *pdn;
> - struct pnv_phb *phb;
> + struct pci_controller *hose = pci_bus_to_host(bus);
> + struct pnv_phb *phb = hose->private_data;
> int ret;
>
> pdn = pci_get_pdn_by_devfn(bus, devfn);
> if (!pdn)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> + return pnv_pci_cfg_write_raw(phb->opal_id, bus->number, devfn,
> +where, size, val);
>
> if (!pnv_pci_cfg_check(pdn))
> return PCIBIOS_DEVICE_NOT_FOUND;
> --
> 2.20.1
>
Reviewed-by: Oliver O'Halloran
where, size, val);
> +
> + if (!ret && (*val == EEH_IO_ERROR_VALUE(size)) &&
> phb->unfreeze_pe)
> + phb->unfreeze_pe(phb, (pe_number == IODA_INVALID_PE) ?
> + phb->ioda.reserved_pe_idx :
> pe_number,
> +OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
> +
> + return ret;
> + }
>
> if (!pnv_pci_cfg_check(pdn))
> return PCIBIOS_DEVICE_NOT_FOUND;
> --
> 2.20.1
>
Reviewed-by: Oliver O'Halloran
On Thu, May 9, 2019 at 3:38 PM Nicholas Piggin wrote:
>
> Andrew Donnellan's on May 9, 2019 3:11 pm:
> > SCOM_DEBUGFS is really not needed for anything other than low-level
> > hardware debugging.
> >
> > opal-prd uses its own interface (/dev/prd) for SCOM access, so it doesn't
> > need SCOM_DEBUG
On Mon, May 13, 2019 at 9:23 PM Masahiro Yamada
wrote:
>
> Commit 5e9dcb6188a4 ("powerpc/boot: Expose Kconfig symbols to wrapper")
> was wrong, but commit e41b93a6be57 ("powerpc/boot: Fix build failures
> with -j 1") was also wrong.
>
> Check-in source files never ever depend on build artifacts.
>
On Mon, May 13, 2019 at 11:56 PM Masahiro Yamada
wrote:
>
> On Mon, May 13, 2019 at 9:33 PM Masahiro Yamada
> wrote:
> >
> > Commit 5e9dcb6188a4 ("powerpc/boot: Expose Kconfig symbols to wrapper")
> > was wrong, but commit e41b93a6be57 ("powerpc/boot: Fix build failures
> > with -j 1") was also w
On Tue, May 28, 2019 at 8:56 AM Shawn Anastasio wrote:
>
> Hello all,
>
> This patch set implements support for user-specified PCI resource
> alignment on the pseries platform for hotplugged PCI devices.
> Currently on pseries, PCI resource alignments specified with the
> pci=resource_alignment co
On Tue, May 28, 2019 at 1:29 PM Stewart Smith wrote:
>
> If the previous comment made sense, continue debugging or call your
> doctor immediately.
>
> Signed-off-by: Stewart Smith
> ---
> arch/powerpc/platforms/powernv/eeh-powernv.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
>
On Tue, May 28, 2019 at 2:09 PM Shawn Anastasio wrote:
>
>
>
> On 5/27/19 11:01 PM, Oliver wrote:
> > On Tue, May 28, 2019 at 8:56 AM Shawn Anastasio wrote:
> >>
> >> Hello all,
> >>
> >> This patch set implements support for user-specified P
On Tue, May 28, 2019 at 2:03 PM Shawn Anastasio wrote:
>
> Introduce a new pcibios function pcibios_ignore_alignment_request
> which allows the PCI core to defer to platform-specific code to
> determine whether or not to ignore alignment requests for PCI resources.
>
> The existing behavior is to
ents
> to big-endian before calling HCALL.
>
> Based on an patch from Oliver O'Halloran
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/platforms/pseries/papr_scm.c | 104 +-
> 1 file changed, 82 insertions(+), 22 deletions(-)
>
> diff
flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
> + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
> + flags |= IORESOURCE_MEM_64;
> flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
> if (addr0 & 0x4000)
> flags |= IORESOURCE_PREFETCH
> --
> 2.17.1
Seems like an oversight that PROBE_ONLY has been papering over for years.
Reviewed-by: Oliver O'Halloran
On Tue, May 7, 2019 at 2:30 PM Sam Bobroff wrote:
>
> Now that EEH support for all devices (on PowerNV and pSeries) is
> provided by the pcibios bus add device hooks, eeh_probe_devices() and
> eeh_addr_cache_build() are redundant and can be removed.
>
> Move the EEH enabled message into it's own f
On Thu, Jun 6, 2019 at 5:17 PM Alistair Popple wrote:
>
> I have been hitting EEH address errors testing this with some network
> cards which map/unmap DMA addresses more frequently. For example:
>
> PHB4 PHB#5 Diag-data (Version: 1)
> brdgCtl:0002
> RootSts:00060020 00402000 a0220008
On Tue, Jun 27, 2017 at 12:33 PM, Michael Ellerman wrote:
> kbuild test robot writes:
>
>> Hi Oliver,
>>
>> [auto build test ERROR on powerpc/next]
>> [also build test ERROR on v4.12-rc6 next-20170623]
>> [if your patch is applied to the wrong git tree, pleas
n 27, 2017 at 08:28:49PM +1000, Oliver O'Halloran wrote:
>> A fairly bare-bones set of device-tree bindings so libnvdimm can be used
>> on powerpc and other, less cool, device-tree based platforms.
>
> ;)
>
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Oli
On Fri, Jun 30, 2017 at 7:28 PM, Anshuman Khandual
wrote:
> On 06/30/2017 12:22 PM, Oliver O'Halloran wrote:
>> Export it so it can be referenced inside a module.
>>
>> Signed-off-by: Oliver O'Halloran
>> ---
>> arch/powerpc/mm/hugetlbpage.c | 1 +
&g
On Thu, Jul 6, 2017 at 8:20 PM, Michael Ellerman wrote:
> Stewart Smith writes:
>> Oliver O'Halloran writes:
>>> diff --git a/arch/powerpc/include/asm/opal-api.h
>>> b/arch/powerpc/include/asm/opal-api.h
>>> index 0e2e57bcab50..cb9c0e6afb33 100644
>
On Fri, Jul 7, 2017 at 10:28 AM, Stewart Smith
wrote:
> Michael Ellerman writes:
>> Stewart Smith writes:
>>> Oliver O'Halloran writes:
>>>> diff --git a/arch/powerpc/include/asm/opal-api.h
>>>> b/arch/powerpc/include/asm/opal-api.h
>>>&
On Mon, Jul 10, 2017 at 9:50 PM, Michael Ellerman wrote:
> Oliver O'Halloran writes:
>
>> The workaround for the CELL timebase bug does not correctly mark cr0 as
>> being clobbered. This can result in GCC making some poor^W completely
>> broken optimisations.
>
&
On Tue, Jul 11, 2017 at 9:53 AM, Dan Williams wrote:
> On Tue, Jun 27, 2017 at 3:28 AM, Oliver O'Halloran wrote:
>> struct device contains the ->of_node pointer so that devices can be
>> assoicated with the device-tree node that created them on DT platforms.
>> libn
nv/opal.c
> index 65c79ec..a4f977f 100644
> --- a/arch/powerpc/platforms/powernv/opal.c
> +++ b/arch/powerpc/platforms/powernv/opal.c
> @@ -889,6 +889,9 @@ static int __init opal_init(void)
> /* Initialise OPAL sensor groups */
> opal_sensor_groups_init();
>
> + /* Initialise OCC driver */
> + opal_pdev_init("ibm,opal-occ-inband-sensors");
> +
> return 0;
> }
> machine_subsys_initcall(powernv, opal_init);
> --
> 1.8.3.1
Overall I'm wondering if we really need a separate driver for this. We
added the /ibm,opal/firmware/exports/ node to handle this sort of
thing so it would be good if we could use that. Do you know what is
going to consume this data in userspace?
Thanks,
oliver
On Thu, Oct 19, 2017 at 10:13 PM, Christophe LEROY
wrote:
>
>
> Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
>>
>> Implement the architecture specific cache maintence functions that make
>> up the "PMEM API". Currently the writeback and inva
On Thu, Oct 19, 2017 at 10:14 PM, Christophe LEROY
wrote:
>
>
> Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
>>
>> Implement the architecture specific portitions of the UACCESS_FLUSHCACHE
>> API. This provides functions for the copy_user_flushcache iterator t
On Tue, Oct 24, 2017 at 7:17 AM, Stephen Bates wrote:
>
>> [3.537780] lpar: Attempting to resize HPT to shift 21
>> [3.539251] Unable to resize hash page table to target order 21: -1
>> [3.541079] Unable to create mapping for hot added memory
>> 0xc0002100..0xc00021000400
On Thu, Oct 26, 2017 at 1:34 AM, Oliver wrote:
> On Tue, Oct 24, 2017 at 7:17 AM, Stephen Bates wrote:
>>
>>> [3.537780] lpar: Attempting to resize HPT to shift 21
>>> [3.539251] Unable to resize hash page table to target order 21: -1
>>> [3.5410
On Thu, Nov 16, 2017 at 5:05 AM, Dan Williams wrote:
> On Wed, Nov 15, 2017 at 9:51 AM, Oliver O'Halloran wrote:
>> We want to be able to cross reference the region and bus devices
>> with the device tree node that they were spawned from. libNVDIMM
>> handles creat
t commit 656ad58ef19e (powerpc/boot: Add OPAL console
>> >to epapr wrappers) adds typedefs for uint32_t and uint64_t to type.h but
>> >doesn't remove the pre-existing (and now duplicate) typedefs from
>> >libfdt_env.h. Fix the error by removing the duplicat typed
On Tue, Mar 20, 2018 at 8:19 PM, Michael Ellerman wrote:
> Oliver O'Halloran writes:
>> diff --git a/arch/powerpc/boot/mpc52xx-psc.c
>> b/arch/powerpc/boot/mpc52xx-psc.c
>> index c2c08633ee35..75470936e661 100644
>> --- a/arch/powerpc/boot/mpc52xx-psc.c
>>
On Tue, Mar 20, 2018 at 8:20 PM, Michael Ellerman wrote:
> Oliver O'Halloran writes:
>
>> Rather than checking the compatible string in serial_driver_init()
>> we call into the driver's init function and wait for a driver to
>> inidicate it bound to the d
On Wed, Mar 21, 2018 at 2:07 PM, Sinan Kaya wrote:
> Hi PPC Maintainers,
>
> We are seeking feedback on the status of relaxed write API implementation.
> What is the motivation for not implementing the relaxed API?
Hmm, good question.
Looks like we've implemented the relaxed_* variants by aliasi
RAM from 8GB to 2GB.
I think there's a known issue with the freescale PCIe root complex
where it can't DMA beyond the 4GB mark. There's a workaround in
the form of limit_zone_pfn() which you can use to put the lower 4GB into
ZONE_DMA32 and allocate from there rather than ZONE_NORMAL.
For details of how to use it have a look at corenet_gen_setup_arch() in
arch/powerpc/platforms/85xx/corenet_generic.c
Hope that helps,
Oliver
On Thu, Mar 22, 2018 at 1:35 AM, David Laight wrote:
>> x86 has compiler barrier inside the relaxed() API so that code does not
>> get reordered. ARM64 architecturally guarantees device writes to be observed
>> in order.
>
> There are places where you don't even need a compile barrier between
> ev
On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert wrote:
> On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
>> On Thu, Mar 22, 2018 at 1:35 AM, David Laight
>> wrote:
>> >> x86 has compiler barrier inside the relaxed() API so that code does not
>> >&g
> normal NC space) while maintaining the ordering between relaxed reads
> and writes. The flip side is a (slight) increased overhead of
> readl_relaxed.
Are there many drivers that actually do writeX() on WC space?
memory-barriers.txt
pretty much says that all bets are off and no ordering guarantees can be assumed
when using readX/writeX on prefetchable IO memory. It seems sketchy enough to
give me some pause, but maybe it works fine elsewhere.
Oliver
ocations
to ZONE_DMA32. Without that the kmemdup() will allocate from any zone
so you'll probably get an unmappable address.
That said, the driver probably shouldn't be using kmemdup() here.
DMA-API.txt pretty explicitly says that drivers should not assume that
dma_map_single() will w
be able
to fix the uses of kmemdup() and kzalloc() in
ath10k_pci_hif_exchange_bmi_msg() and call it a day. Auditing the
other uses of dma_map_single() to see if they're using kmalloc()
memory might be a good idea too.
Anyway this is probably something you're better off taking to the ath1
On Sat, Mar 24, 2018 at 4:07 AM, Dan Williams wrote:
> On Fri, Mar 23, 2018 at 1:12 AM, Oliver O'Halloran wrote:
>> This patch adds peliminary device-tree bindings for the NVDIMM driver.
>
> *preliminary
>
>> Currently this only supports one bus (created at probe t
On Tue, Mar 27, 2018 at 9:24 AM, Rob Herring wrote:
> On Fri, Mar 23, 2018 at 07:12:09PM +1100, Oliver O'Halloran wrote:
>> Add device-tree binding documentation for the nvdimm region driver.
>>
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Oliver O
On Thu, Mar 29, 2018 at 9:14 AM, Russell King - ARM Linux
wrote:
> On Wed, Mar 28, 2018 at 02:04:22PM -0500, Rob Landley wrote:
>>
>>
>> On 03/28/2018 11:48 AM, Russell King - ARM Linux wrote:
>> > On Wed, Mar 28, 2018 at 10:58:51AM -0500, Rob Landley wrote:
>> >> On 03/28/2018 10:26 AM, Shea Levy
On Thu, Mar 29, 2018 at 4:06 AM, Rob Herring wrote:
> On Tue, Mar 27, 2018 at 9:53 AM, Oliver wrote:
>> On Tue, Mar 27, 2018 at 9:24 AM, Rob Herring wrote:
>>> On Fri, Mar 23, 2018 at 07:12:09PM +1100, Oliver O'Halloran wrote:
>>>> Add device-tree binding
On Wed, Apr 4, 2018 at 10:07 PM, Balbir Singh wrote:
> On Tue, 3 Apr 2018 10:37:51 -0700
> Dan Williams wrote:
>
>> On Tue, Apr 3, 2018 at 7:24 AM, Oliver O'Halloran wrote:
>> > Add device-tree binding documentation for the nvdimm region driver.
>> &g
On Thu, Apr 5, 2018 at 5:14 PM, Balbir Singh wrote:
> The pmem infrastructure uses memcpy_mcsafe in the pmem
> layer so as to convert machine check excpetions into
> a return value on failure in case a machine check
> exception is encoutered during the memcpy.
>
> This patch largely borrows from t
On Thu, Apr 5, 2018 at 12:21 AM, Dan Williams wrote:
> On Wed, Apr 4, 2018 at 7:04 AM, Oliver wrote:
>> On Wed, Apr 4, 2018 at 10:07 PM, Balbir Singh wrote:
>>> On Tue, 3 Apr 2018 10:37:51 -0700
>>> Dan Williams wrote:
>>>
>>>> On Tue,
On Thu, Apr 5, 2018 at 10:11 PM, Michael Ellerman wrote:
> Oliver writes:
> ...
>>
>> For context Balbir is working with me on some of the pmem stuff. You
>> probably want an Ack from Rob rather than one of us.
>
> I'll ack it if you make all the niggly nit
On Fri, Apr 6, 2018 at 12:43 AM, Dan Williams wrote:
> On Thu, Apr 5, 2018 at 5:43 AM, Oliver wrote:
>> On Thu, Apr 5, 2018 at 10:11 PM, Michael Ellerman
>> wrote:
>>> Oliver writes:
>>> ...
>>>>
>>>> For context Balbir is working wit
of negative impact on
end users by merging it now. At the very least it lets the rest of the
kernel development community know that changes affecting zones should
also be tested on powerpc.
Thanks,
Oliver
On Fri, May 6, 2016 at 3:13 PM, Anshuman Khandual
wrote:
> On 05/05/2016 08:18 PM, Aneesh
On Mon, May 9, 2016 at 4:28 PM, Balbir Singh wrote:
>
>
> On 04/05/16 17:37, Oliver O'Halloran wrote:
>> POWER ISA v3 adds large decrementer (LD) mode of operation which increases
>> the size of the decrementer register from 32 bits to an implementation
>&g
memory cannot be used for kernel allocations. I've already
submitted a patch to fix the powerpc specific bits, but I figured this should
be fixed too.
oliver
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On Mon, May 30, 2016 at 7:15 PM, Mel Gorman wrote:
> On Thu, May 26, 2016 at 02:21:42PM -0700, Andrew Morton wrote:
>> On Thu, 5 May 2016 17:57:13 +1000 "Oliver O'Halloran"
>> wrote:
>>
>> > As a part of memory initialisation the architecture
On Thu, May 26, 2016 at 9:29 PM, Safa Hamza wrote:
>
> thanks for replying, I tried a powerpc cross compiler from the list you have
> send but I always got this error
>
> VDSO32L arch/powerpc/kernel/vdso32/vdso32.so.dbg
> /home/marwa/Bureau/lauterbach/powerpc/gcc-4.6.3-nolibc/powerpc64-linux/bin/
On Tue, May 31, 2016 at 4:25 PM, Michael Neuling wrote:
> On Tue, 2016-05-10 at 14:57 +1000, Oliver O'Halloran wrote:
>> static int decrementer_set_next_event(unsigned long evt,
>> struct clock_event_device *dev);
>> @@ -5
On Wed, Jun 1, 2016 at 4:23 PM, Michael Neuling wrote:
> On Tue, 2016-05-31 at 17:16 +1000, Oliver O'Halloran wrote:
>> +#define IS_LD_ENABLED(reg) \
>> + mfspr reg,SPRN_LPCR; \
>> + andis. reg,reg,(LPCR_LD >> 16);
>
>
On Thu, Jun 23, 2016 at 6:02 PM, Denis Kirjanov wrote:
> On 6/23/16, Oliver O'Halloran wrote:
>> +static void __init set_decrementer_max(void)
>> +{
>> + struct device_node *cpu;
>> + const __be32 *fp;
>> + u64 bits = 32;
>> +
>> +
It would appear I did. Oh well, shouldn't have been in such a rush to
get to the pub.
On Fri, Jun 24, 2016 at 9:57 PM, Benjamin Herrenschmidt
wrote:
> On Fri, 2016-06-24 at 17:41 +1000, Oliver O'Halloran wrote:
>> This patch adds an OPAL console backend to the powerpc boot wr
On Mon, Jun 27, 2016 at 2:38 PM, Stewart Smith
wrote:
> Oliver O'Halloran writes:
> One thing to think of is if we really need anything printed except the
> error message. Out of these three lines of output (for a corrupted
> zImage.epapr), only the last line gives any
On Tue, Jul 5, 2016 at 10:24 AM, Michael Neuling wrote:
> On Mon, 2016-07-04 at 16:09 +1000, Michael Ellerman wrote:
>> On Mon, 2016-04-07 at 00:44:04 UTC, Oliver O'Halloran wrote:
>> >
>> > This patch adds the kernel command line parameter "no_tb_segs"
value of VRSAVE is used to determine if altivec is being used
in several code paths.
Signed-off-by: Oliver O'Halloran
---
arch/powerpc/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 82
value of VRSAVE is used to determine if altivec is being used
in several code paths.
Signed-off-by: Oliver O'Halloran
Signed-off-by: Anton Blanchard
Fixes: 152d523e6307 ("powerpc: Create context switch helpers save_sprs() and
restore_sprs()")
Cc: sta...@vger.kernel.org
---
ar
property
is not supplied then the traditional decrementer width of 32 bits is
assumed and LD mode is disabled.
This patch was based on inital work by Jack Miller.
Signed-off-by: Oliver O'Halloran
Cc: Jack Miller
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/include/asm/time.h
decrementer registers. These macros will return the current
decrementer value as a 64 bit quantity regardless of the Host CPU or
guest decrementer operating mode. Additionally this patch corrects several
uses of decrementer values that assume a 32 bit register width.
Signed-off-by: Oliver O'Hallora
I think this bug can only be triggered if the instruction to
simulate is malformed. The switch in the else case only handles
the zero and one case, but it extracts bits 4:1 from the
instruction word so it may be other values. It's pretty minor, but
a bug is a bug.
Signed-off-by: Oliver O
-by: Oliver O'Halloran
---
arch/powerpc/lib/sstep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index dc885b3..e25f73c 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -925,6 +925,7 @@ int __kprobes analyse_
-by: Oliver O'Halloran
---
arch/powerpc/lib/sstep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index dc885b3..e25f73c 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -925,6 +925,7 @@ int __kprobes analyse_
The PowerNV platform depends on CONFIG_PPC64 so this #ifdef in the middle
of platforms/powernv/pci.c really doesn't need to be there.
Signed-off-by: Oliver O'Halloran
---
arch/powerpc/platforms/powernv/pci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/platfor
On Wed, 2019-03-20 at 13:58 +1100, Sam Bobroff wrote:
> The PHB flag, PNV_PHB_FLAG_EEH, is set (on PowerNV) individually on
> each PHB once the EEH subsystem is ready. It is the only use of the
> flags member of the phb struct.
>
> However there is no need to store this separately on each PHB, so
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