PCI: Work around PCIe link training failures

2024-07-22 Thread Matthew W Carlis
Sorry to resurrect this one, but I was wondering why the PCI device ID in drivers/pci/quirks.c for the ASMedia ASM2824 isn't checked before forcing the link down to Gen1... We have had to revert this patch during our kernel migration due to it interacting poorly with at least one older Gen3 PLX PCI

PCI: Work around PCIe link training failures

2024-07-24 Thread Matthew W Carlis
Sorry for belated response. I wasn't really sure when you first asked & I still only have a 'hand wavy' theory here. I think one thing that is getting us in trouble is when we turn the endpoint device on, then off, wait for a little while then turn it back on. It seems that the port here in this ca

PCI: Work around PCIe link training failures

2024-07-26 Thread Matthew W Carlis
On Mon, 22 Jul 2024, Maciej W. Rozycki wrote: > The main reason is it is believed that it is the downstream device > causing the issue, and obviously you can't fetch its ID if you can't > negotiate link so as to talk to it in the first place. Have had some more time to look into this issue. So, I

PCI: Work around PCIe link training failures

2024-07-29 Thread Matthew W Carlis
On Mon, 29 July 2024, Ilpo Järvinen wrote: > The most obvious solution is to not leave the speed at Gen1 on failure in > Target Speed quirk but to restore the original Target Speed value. The > downside with that is if the current retraining interface (function) is > used, it adds delay. Tends to

PCI: Work around PCIe link training failures

2024-08-05 Thread Matthew W Carlis
Hello again. I just realized that my first response to this thread two weeks ago was not actually starting from the end of the discussion. I hope I found it now... Must say sorry for this I am still figuring out how to follow these threads. I need to ask if we can either revert this patch or only m

PCI: Work around PCIe link training failures

2024-08-07 Thread Matthew W Carlis
On Tues, 06 Aug 2024 Bjorn Helgaas wrote: > it does seem like this series made wASMedia ASM2824 work better but > caused regressions elsewhere, so maybe we just need to accept that > ASM2824 is slightly broken and doesn't work as well as it should. One of my colleagues challenged me to provide a m

PCI: Work around PCIe link training failures

2024-08-07 Thread Matthew W Carlis
On Wed, 7 Aug 2024 22:29:35 +1000 Oliver O'Halloran Wrote > My read was that Matt is essentially doing a surprise hot-unplug by > removing power to the card without notifying the OS. I thought the > LBMS bit wouldn't be set in that case since the link goes down rather > than changes speed, but the

PCI: Work around PCIe link training failures

2024-08-15 Thread Matthew W Carlis
Sorry for the delay in my responses here I had some things get in my way. On Fri, 9 Aug 2024 09:13:52 Oliver O'Halloran wrote: > Ok? If we have to check for DPC being enabled in addition to checking > the surprise bit in the slot capabilities then that's fine, we can do > that. The question to b

PCI: Work around PCIe link training failures

2024-10-01 Thread Matthew W Carlis
I just wanted to follow up with our testing results for the mentioned patches. It took me a while to get them running in our test pool, but we just got it going yesterday and the initial results look really good. We will continue running them in our testing from now on & if any issues come up I'll

PCI: Work around PCIe link training failures

2025-06-10 Thread Matthew W Carlis
Hello again.. It looks like there are specific system configurations that are extremely likely to have issues with this patch & result in undesirable system behavior.. Specifically hot-plug systems with side-band presence detection & without Power Controls (i.e PwrCtrl-) given to config space. I