Le 30/08/2017 à 23:01, Benjamin Herrenschmidt a écrit :
On Wed, 2017-08-30 at 15:59 +0200, Frederic Barrat wrote:
It's not clear why it makes sense for these to be empty. Either for the
general idea of the "flush_all_mm()" API, or for your intended use by
CXL.
I was not too
With the optimizations introduced by commit a46cc7a90fd8
("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no
longer flushes the page walk cache with radix. This patch introduces
flush_all_mm(), which flushes everything, tlb and pwc, for a given mm.
Signed-off-by: Frede
l on hash.
Signed-off-by: Frederic Barrat
Fixes: f24be42aab37 ("cxl: Add psl9 specific code")
---
Changelog:
v3: don't decrement active cpus count with hash, as we don't know how to flush
v2: Replace flush_tlb_mm() by the new flush_all_mm() to flush the TLBs
and PWCs (thanks to
d a call to smp_wmb() after setting the bit [Michael Ellerman]
---
Acked-by: Frederic Barrat
drivers/misc/cxl/native.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 4a82c313cf71..75df74d59527 100644
--- a/drivers/misc/
Le 05/09/2017 à 05:57, Alistair Popple a écrit :
The nest mmu required an explicit flush as a tlbi would not flush it in the
same way as the core. However an alternate firmware fix exists which should
eliminate the need for this flush, so instead add a device-tree property
(ibm,nmmu-flush) on t
er item is capp recovery, which is still
being worked on, but any change required there would hopefully be
limited to skiboot.
With the above:
Acked-by: Frederic Barrat
Fred
Changelog[v2]
- Rebase to latest upstream.
- Update the function is_page_fault()
---
drivers/misc/c
the NVLink2 PHB to enable it only if required.
Signed-off-by: Alistair Popple
---
FWIW,
Reviewed-by: Frederic Barrat
Changes for v2:
- Use mm_context_add_copro()/mm_context_remove_copro() instead
of inc_mm_active_cpus()/dec_mm_active_cpus()
arch/powerpc/platforms/powernv/npu-dma.c
Le 08/09/2017 à 08:56, Nicholas Piggin a écrit :
On Sun, 3 Sep 2017 20:15:13 +0200
Frederic Barrat wrote:
The PSL and nMMU need to see all TLB invalidations for the memory
contexts used on the adapter. For the hash memory model, it is done by
making all TLBIs global as soon as the cxl
Le 13/09/2017 à 06:04, Alistair Popple a écrit :
+static inline void hash__local_flush_all_mm(struct mm_struct *mm)
+{
+ /*
+* There's no Page Walk Cache for hash, so what is needed is
+* the same as flush_tlb_mm(), which doesn't really make sense
+* with hash. So
refcount leak.
Fixes: f24be42aab37 ("cxl: Add psl9 specific code")
Signed-off-by: Miaoqian Lin
Indeed. Thanks!
Acked-by: Frederic Barrat
Fred
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 3d
supported on the Power10 processor. We aren't aware of any users who are
likely to be using recent kernels.
Thanks to Mikey Neuling, Ian Munsie, Daniel Axtens, Frederic Barrat,
Christophe Lombard, Philippe Bergheaud, Vaibhav Jain and Alastair
D'Silva for their work on this driver over
Manoj Kumar for their work on
this driver over the years.
Signed-off-by: Andrew Donnellan
Reviewed-by: Frederic Barrat "
Fred
Acked-by: Frederic Barrat
Fred
---
Documentation/ABI/{testing => obsolete}/sysfs-class-cxl | 3 +++
MAINTAINERS | 4 ++--
drivers/misc/cxl/Kconfig| 6 --
drivers/misc/cxl/of.c
available.
Add a warning message on probe and change Kconfig to label the driver as
deprecated and not build the driver by default.
Signed-off-by: Andrew Donnellan
Reviewed-by: Frederic Barrat
Fred
---
drivers/scsi/cxlflash/Kconfig | 6 --
drivers/scsi/cxlflash/main.c | 2 ++
2
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