this posix compatibility issue.
Fixes: 996f9e0f93f162 ("selftests/powerpc: Fix eeh-basic.sh exit codes")
Signed-off-by: Po-Hsu Lin
---
With the above,
Reviewed-by: Frederic Barrat
Thanks!
tools/testing/selftests/powerpc/eeh/eeh-basic.sh | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 29/01/2021 09:25, Yang Li wrote:
Fix the following coccicheck warning:
./drivers/misc/cxl/sysfs.c:181:48-53: WARNING: conversion to bool not
needed here
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
Thanks!
Acked-by: Frederic Barrat
drivers/misc/cxl/sysfs.c | 2 +-
1
Le 02/06/2020 à 09:05, Andrew Donnellan a écrit :
The CXL_AFU_DRIVER_OPS Kconfig option was added to coordinate merging of
new features. It no longer serves any purpose, so remove it.
Signed-off-by: Andrew Donnellan
Acked-by: Frederic Barrat
---
v1->v2:
- keep CXL_LIB for now
: b087e6190ddc ("cxl: Export optional AFU configuration record in sysfs")
Reported-by: Hulk Robot
Signed-off-by: Wang Hai
Indeed, a call to kobject_put() is needed when the init fails.
Thanks!
Acked-by: Frederic Barrat
---
drivers/misc/cxl/sysfs.c | 2 +-
1 file changed, 1 insertion(+),
Le 13/06/2020 à 02:41, Fenghua Yu a écrit :
PASID is defined as "int" although it's a 20-bit value and shouldn't be
negative int. To be consistent with type defined in iommu, define PASID
as "unsigned int".
It looks like this patch was considered because of the use of 'pasid' in
variable o
Le 18/06/2020 à 17:37, Fenghua Yu a écrit :
The first 3 patches clean up pasid and flag defitions to prepare for
following patches.
If you think this patch can be dropped, we will drop it.
Yes, I think that's the case.
Thanks,
Fred
From: Philippe Bergheaud
Some opencapi FPGA images allow to control if the FPGA should be reloaded
on the next adapter reset. If it is supported, the image specifies it
through a Vendor Specific DVSEC in the config space of function 0.
Signed-off-by: Philippe Bergheaud
Signed-off-by: Frederic
iewed-by: Frederic Barrat
arch/powerpc/include/asm/tce.h | 8 --
arch/powerpc/platforms/pseries/iommu.c | 39 +++---
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index db5f
On 16/07/2021 10:27, Leonardo Bras wrote:
@@ -1099,18 +1105,13 @@ int iommu_take_ownership(struct iommu_table *tbl)
for (i = 0; i < tbl->nr_pools; i++)
spin_lock_nest_lock(&tbl->pools[i].lock, &tbl->large_pool.lock);
- iommu_table_release_pages(tbl);
-
- if (!
ies_alloc_table(node);
+ if (table_group->tables[0])
+ return table_group;
Nitpick: for readability, we'd usually expect the error path to be
detected with the if statement and keep going on the good path, and here
the code does the opposite. No big deal though, so
: Frederic Barrat
arch/powerpc/platforms/pseries/iommu.c | 32 +-
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/iommu.c
b/arch/powerpc/platforms/pseries/iommu.c
index 33d82865d6e6..712d1667144a 100644
--- a/arch/powerpc
ff-by: Leonardo Bras
Reviewed-by: Alexey Kardashevskiy
---
Looks good to me
Reviewed-by: Frederic Barrat
arch/powerpc/platforms/pseries/iommu.c | 36 +-
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/iommu.c
b
On 16/07/2021 10:27, Leonardo Bras wrote:
Code used to create a ddw property that was previously scattered in
enable_ddw() is now gathered in ddw_property_create(), which deals with
allocation and filling the property, letting it ready for
of_property_add(), which now occurs in sequence.
This
we need the iommu_table_ops to be
declared before used, declare iommu_table_lpar_multi_ops and
iommu_table_pseries_ops to before their respective iommu_table_setparms*().
Signed-off-by: Leonardo Bras
---
Looks good
Reviewed-by: Frederic Barrat
arch/powerpc/platforms/pseries/iommu.c |
On 16/07/2021 10:27, Leonardo Bras wrote:
Update remove_dma_window() so it can be used to remove DDW with a given
property name.
This enables the creation of new property names for DDW, so we can
have different usage for it, like indirect mapping.
Signed-off-by: Leonardo Bras
Reviewed-by: A
e.
Signed-off-by: Leonardo Bras
Reviewed-by: Alexey Kardashevskiy
---
Reviewed-by: Frederic Barrat
arch/powerpc/platforms/pseries/iommu.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/iommu.c
b/ar
On 16/07/2021 10:27, Leonardo Bras wrote:
So far it's assumed possible to map the guest RAM 1:1 to the bus, which
works with a small number of devices. SRIOV changes it as the user can
configure hundreds VFs and since phyp preallocates TCEs and does not
allow IOMMU pages bigger than 64K, it ha
ry to rename all names and debug/info
messages to reflect that it can be used for both kinds of mapping.
This should cause no behavioural change, just adjust naming.
Signed-off-by: Leonardo Bras
---
LGTM:
Reviewed-by: Frederic Barrat
arch/powerpc/platforms/pseries/iommu.c
On 21/07/2021 05:32, Alexey Kardashevskiy wrote:
+ struct iommu_table *newtbl;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pci->phb->mem_resources); i++) {
+ const unsigned long mask = IORESOURCE_MEM_64 |
IORESOURCE_MEM;
+
+ /* Look for MMIO32 */
+
Hi,
The PCI p2p and tunnel code is used by the Mellanox CX5 driver, at least
their latest, out of tree version, which is used for CORAL. My
understanding is that they'll upstream it at some point, though I don't
know what their schedule is like.
Fred
Le 26/04/2019 à 14:49, Christoph Hell
If we couldn't fully init a context, we were leaking memory.
Fixes: b9721d275cc2 ("ocxl: Allow external drivers to use OpenCAPI contexts")
Signed-off-by: Frederic Barrat
---
drivers/misc/ocxl/context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/ocxl/cont
Le 20/05/2019 à 03:45, Andrew Donnellan a écrit :
On 18/5/19 12:20 am, Frederic Barrat wrote:
If we couldn't fully init a context, we were leaking memory.
Fixes: b9721d275cc2 ("ocxl: Allow external drivers to use OpenCAPI
contexts")
Signed-off-by: Frederic Barrat
A
If we couldn't fully init a context, we were leaking memory.
Fixes: b9721d275cc2 ("ocxl: Allow external drivers to use OpenCAPI contexts")
Signed-off-by: Frederic Barrat
---
Changelog:
v2: reset context pointer in case of allocation failure (Andrew)
drivers/misc/ocxl/context.c
lt n' is
redundant.
...
Signed-off-by: Bartlomiej Zolnierkiewicz
---
for cxl and ocxl:
Acked-by: Frederic Barrat
drivers/misc/Kconfig | 10 --
drivers/misc/altera-stapl/Kconfig |1 -
drivers/misc/c2port/Kconfig |2 --
drivers/misc/cb710/K
t's an NPU problem
and report which FIR and which bit were raised if opal gave us the
information.
Signed-off-by: Frederic Barrat
---
Could be merged independently from (the opal-api.h change is already
in the skiboot tree), but works better with, the matching skiboot
change:
http://patch
Le 23/05/2019 à 15:45, Michael Ellerman a écrit :
Frederic Barrat writes:
If the kernel is notified of an HMI caused by the NPU2, it's currently
not being recognized and it logs the default message:
Unknown Malfunction Alert of type 3
The NPU on Power 9 has 3 Fault Isol
Yamada
---
Thanks!
Acked-by: Frederic Barrat
include/uapi/misc/ocxl.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/uapi/misc/ocxl.h b/include/uapi/misc/ocxl.h
index 97937cfa3baa..6d29a60a896a 100644
--- a/include/uapi/misc/ocxl.h
+++ b/include
ory but as we
start seeing (non-LPC) AFU images using the new template, this patch
updates the config space parsing code to avoid spitting a warning.
Signed-off-by: Alastair D'Silva
Signed-off-by: Frederic Barrat
---
mpe: this patch is originally from Alastair. I added some minor
tweaking,
Le 12/06/2019 à 12:02, Greg Kroah-Hartman a écrit :
On Wed, Jun 12, 2019 at 11:51:21AM +0200, Arnd Bergmann wrote:
On Tue, Jun 11, 2019 at 8:13 PM Greg Kroah-Hartman
wrote:
@@ -64,8 +64,6 @@ int cxl_debugfs_adapter_add(struct cxl *adapter)
snprintf(buf, 32, "card%i", adapter->ada
On 09/02/2022 04:24, Cai Huoqing wrote:
Replace "struct list_head head = LIST_HEAD_INIT(head)" with
"LIST_HEAD(head)" to simplify the code.
Signed-off-by: Cai Huoqing
---
Thanks!
Acked-by: Frederic Barrat
drivers/misc/ocxl/link.c | 2 +-
1 file changed, 1 inse
parameters.
Signed-off-by: Vaibhav Jain
---
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h| 3 ---
drivers/misc/cxl/native.c | 56 ++-
drivers/misc/cxl/pci.c| 44 -
3 files changed, 55 insertions(+), 48
Hi Vaibhav,
There's one thing bugging me here, see below
Le 14/03/2017 à 05:06, Vaibhav Jain a écrit :
This patch introduces a new afu sysfs attribute named afu_desc. This
binary attribute provides access to raw contents of the afu descriptor
to user-space. Direct access to afu descriptor is u
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
The PSL Process and Thread Identification Register is onl
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
The mm_struct corresponding to the current task is acquired each time
an interrupt is raised. So to simplify the code, we only get the
mm_struct when attaching an AFU context to the process.
The mm_count reference is increased to ensure that t
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB.
- Attach process for dedicated/directed models.
-
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
--
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
The PSL Process and Thread Identification Register is onl
Le 14/03/2017 à 12:08, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translatio
Another thought about that patch. Now that we keep track of the mm
associated to a context, I think we can simplify slightly the function
_cxl_slbia() in main.c, where we look for the mm based on the pid. We
now have the information readily available.
Fred
Le 14/03/2017 à 12:08, Christophe
till sends local TLBIs, as found out the hard way recently.
This patch fixes it by following the same logic as previously: if the
cxl driver is active, the local TLBIs are 'upgraded' to global.
Fixes: 4c6d9acce1f4 ("powerpc/mm: Add hooks for cxl")
Cc: sta...@vger.kernel.org
will be used by the following patches.
Signed-off-by: Christophe Lombard
---
Acked-by: Frederic Barrat
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 91f6459..e82a207 100644
--- a/drivers/misc/cxl/pci.c
+++ b
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment. These two fields
are renamed to 'reserved' to avoid undef
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The mm_struct corresponding to the current task is acquired each time
an interrupt is raised. So to simplify the code, we only get the
mm_struct when attaching an AFU context to the process.
The mm_count reference is increased to ensure that t
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB.
- Attach process for dedicated/directed models.
-
: Christophe Lombard
---
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h | 26 +-
drivers/misc/cxl/debugfs.c | 6 +++---
drivers/misc/cxl/guest.c | 2 +-
drivers/misc/cxl/irq.c | 2 +-
drivers/misc/cxl/native.c | 12 ++--
drivers/mis
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
Le 28/03/2017 à 17:14, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translatio
Hi Vaibhav,
I like the simplified version better. However, I think it breaks
cxlflash's recovery. With this patch, we are also unlocking the adapter
later. It doesn't matter when the driver initializes the first time, but
on EEH, we now call the "slot reset" callback of the virtual device
whi
evice-drivers.
Cc: sta...@vger.kernel.org
Fixes: 70b565bbdb91("cxl: Prevent adapter reset if an active context exists")
Reported-by: Andrew Donnellan
Signed-off-by: Vaibhav Jain
---
Pending test result from cxl-flash:
Acked-by: Frederic Barrat
Change-Log:
v3..v4
- Moved the call to
will be used by the following patches.
Signed-off-by: Christophe Lombard
---
Acked-by: Frederic Barrat
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index b27ea98..1f4c351 100644
--- a/drivers/misc/cxl/pci.c
+++ b
7;reserved' to avoid undefined behavior on
bare-metal. The PSL Process and Thread Identification Register
(CXL_PSL_PID_TID_An) is only used when attaching a dedicated process
for PSL8 only. This register goes away in CAIA2.
Signed-off-by: Christophe Lombard
---
Acked-by: Frederic Barrat
), of
the structure cxl_context, is removed because it's no longer useful.
Signed-off-by: Christophe Lombard
---
Thanks for the update, I think it looks good now.
Acked-by: Frederic Barrat
drivers/misc/cxl/api.c | 17 +--
drivers/misc/cxl/context.c | 21 +++--
driver
.
- Handle psl interrupts.
- Debug registers for the adapter and the afu.
- Traces.
Each environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
---
Acked-by: Frederic Barrat
drivers
: Christophe Lombard
---
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h | 26 ++--
drivers/misc/cxl/debugfs.c | 6 ++---
drivers/misc/cxl/guest.c | 2 +-
drivers/misc/cxl/irq.c | 2 +-
drivers/misc/cxl/native.c | 12 +-
drivers/mis
splitting long
strings, but that's minor. And the rest looks ok.
I'll do the last patch tomorrow.
Acked-by: Frederic Barrat
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35 +++--
drivers/misc/cxl/debugfs.c | 6 +++--
dr
Le 11/04/2017 à 12:40, Michael Ellerman a écrit :
Frederic Barrat writes:
Le 05/04/2017 à 13:35, Vaibhav Jain a écrit :
During an eeh event when the cxl card is fenced and card sysfs attr
perst_reloads_same_image is set following warning message is seen in the
kernel logs:
[ 60.622727
Le 07/04/2017 à 16:11, Christophe Lombard a écrit :
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translatio
Le 12/04/2017 à 09:52, Andrew Donnellan a écrit :
On 08/04/17 00:11, Christophe Lombard wrote:
+static u32 get_phb_index(struct device_node *np)
{
u32 phb_index;
if (of_property_read_u32(np, "ibm,phb-index", &phb_index))
-return 0;
+return -ENODEV;
Function is uns
- Memory Context ID
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard
Acked-by: Frederic Barrat
---
Documentation
igned-off-by: Vaibhav Jain
---
Looks ok to me. At least we are consistent with what is done in
cxl_vphb_error_detected()
Acked-by: Frederic Barrat
drivers/misc/cxl/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers
Le 26/04/2017 à 08:40, Alastair D'Silva a écrit :
From: Alastair D'Silva
In some situations, a faulty AFU slice may create an interrupt storm,
rendering the machine unusable. Since these interrupts are informational
only, present the interrupt once, then mask it off to prevent it from
being r
_An_IRQ_MASKS ( \
+ CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudup_mask |
CXL_PSL_SERR_An_afuov_mask | \
+ CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask |
CXL_PSL_SERR_An_llcmdis_mask | \
+ CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask |
CXL_PSL_SERR_An_afudup_mask)
+
it off to
prevent it from being retriggered until the AFU is reset.
Signed-off-by: Alastair D'Silva
---
Thanks!
Acked-by: Frederic Barrat
Changelog:
v4:
Fix duplicate/missing entries in aggregate macros
Minor textual changes
v3
Add CXL_PSL_SERR_An_IRQS, CXL_PSL_SE
U and CAPP/PSL. The NPU and the PSL keep their own
translation cache so they need to see all the TLBIs for those
contexts.
Signed-off-by: Frederic Barrat
---
arch/powerpc/include/asm/book3s/64/mmu.h | 9 +
arch/powerpc/include/asm/tlb.h | 10 --
arch/powerpc/mm/mmu_contex
contexts actually used by the device.
So mark the contexts being attached to the cxl adapter as requiring
global TLBIs.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/api.c | 5 -
drivers/misc/cxl/file.c | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers
sed by the card.
Alistair: for nvlink2, it is my understanding that all the required
invalidations are already in place through software mmio/ATSD, i.e. this
patch is not useful for you.
Submitting as an RFC, since I don't get to touch mmu.h everyday and
would like to probe people's reacti
Le 04/05/2017 à 08:41, Aneesh Kumar K.V a écrit :
Frederic Barrat writes:
Introduce a new 'flags' attribute per context and define its first bit
to be a marker requiring all TLBIs for that context to be broadcasted
globally. Once that marker is set on a context, it cannot be remo
Le 05/05/2017 à 07:34, Dan Carpenter a écrit :
We should unlock if get_cxl_adapter() fails.
Fixes: 594ff7d067ca ("cxl: Support to flash a new image on the adapter from a
guest")
Signed-off-by: Dan Carpenter
Acked-by: Frederic Barrat
Thanks!
Fred
diff --git a/driver
Le 04/05/2017 à 09:39, Balbir Singh a écrit :
On Wed, 2017-05-03 at 16:29 +0200, Frederic Barrat wrote:
The PSL needs to see all TLBI pertinent to the memory contexts used on
the cxl adapter. For the hash memory model, it was done by making all
TLBIs global as soon as the cxl driver is in us
Le 04/05/2017 à 11:42, Michael Ellerman a écrit :
Frederic Barrat writes:
Introduce a new 'flags' attribute per context and define its first bit
to be a marker requiring all TLBIs for that context to be broadcasted
globally. Once that marker is set on a context, it cannot be remo
pci_dev *dev);
int pnv_pci_set_p2p_receiver(struct pci_dev *dev);
It uses a new OPAL call, as the configuration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat
---
Need skiboot patch:
http://patchwork.ozlabs.org/patch/768613/
arch/powerpc/include/asm/opal-api.h
Le 02/06/2017 à 11:35, Vaibhav Jain a écrit :
During an eeh call to cxl_remove can result in double free_irq of
psl,slice interrupts. This can happen if perst_reloads_same_image == 1
and call to cxl_configure_adapter() fails during slot_reset
callback. In such a case we see a kernel oops with f
Fix error path if we can't copy user structure on
CXL_IOCTL_START_WORK ioctl.
Signed-off-by: Frederic Barrat
Cc: sta...@vger.kernel.org
---
drivers/misc/cxl/file.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/cxl/file.c b/drivers/misc/cxl/file.c
---
Thanks for the correction.
Acked-by: Frederic Barrat
Fred
Changelog:
v2:
- Use psl_hwirq instead of psl_virq to find irq mapping in
cxl_native_release_psl_irq as pointed out by Fred.
Re-send:
- Added stable to recipients
---
drivers/misc/cxl/native.c | 14 +++---
1 file ch
Le 06/06/2017 à 11:20, Michael Ellerman a écrit :
Frederic Barrat writes:
Fix error path if we can't copy user structure on
CXL_IOCTL_START_WORK ioctl.
To be clear the error is that returning via the out label will unlock
cxl->status_mutex, which has not been locked.
Please spel
Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK
ioctl. We shouldn't unlock the context status mutex as it was not
locked (yet).
Signed-off-by: Frederic Barrat
Cc: sta...@vger.kernel.org
Fixes: 0712dc7e73e5 ("cxl: Fix issues when unmapping contexts"
Salut Christophe,
It looks pretty good, but checkpatch complains about 1 or 2 items worth
fixing.
2 small remarks below.
Le 09/06/2017 à 12:09, Christophe Lombard a écrit :
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new
IPI to only cpus in the mm cpumask, to make sure there
are no parallel lockless page table walk.
Add the CAPI fault handling cpu to the mm cpumask so that we can do the lockless
page table walk while inserting hash page table entries.
Signed-off-by: Aneesh Kumar K.V
---
Reviewed-by: Frederic
) to handle the checkout response status.
- Add comments.
Signed-off-by: Christophe Lombard
---
Looks good to me, thanks!
Acked-by: Frederic Barrat
drivers/misc/cxl/context.c | 6 +++---
drivers/misc/cxl/cxl.h | 18 +-
drivers/misc/cxl/fault.c | 23 +++---
Salut Christophe,
A few comments below, nothing major...
Le 14/06/2017 à 15:29, Christophe Lombard a écrit :
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service Layer) is a stripp
Le 16/06/2017 à 09:13, Andrew Donnellan a écrit :
+config CXL_LIB
+bool
+default n
+
How necessary is this? Are there any drivers using cxllib that we're
trying to get in during this cycle?
That was a Mellanox request, so that they can enable code in their
driver. Like we've done
ONTEXT_GLOBAL_TLBI -> MM_GLOBAL_TLBIE
- add memory barriers to make sure the device doesn't miss any TLBI
- also add barrier for the hash implemention to fix the same issue
Frederic Barrat (3):
powerpc/mm: Add marker for contexts requiring global TLB invalidations
cxl: Mark context requiri
U and CAPP/PSL. The NPU and the PSL keep their own translation cache
so they need to see all the TLBIs for those contexts.
Signed-off-by: Frederic Barrat
---
arch/powerpc/include/asm/book3s/64/mmu.h | 18 ++
arch/powerpc/include/asm/tlb.h | 23 +--
arch/
contexts actually used by the device.
So mark the contexts being attached to the cxl adapter as requiring
global TLBIs.
Signed-off-by: Frederic Barrat
---
drivers/misc/cxl/api.c | 12 ++--
drivers/misc/cxl/file.c | 12 ++--
2 files changed, 20 insertions(+), 4 deletions(-)
diff
xt to the device, therefore we are
exposed to re-ordering. It is highly unlikely as the use count for the
driver is incremented on open() and the attachment to the device
happens on a different system call (ioctl)
Signed-off-by: Frederic Barrat
---
include/misc/cxl-base.h | 18 +-
1
Salut Christophe,
Since there's a respin, 2 details below.
diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c
new file mode 100644
index 000..4f4c5ca
--- /dev/null
+++ b/drivers/misc/cxl/cxllib.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2017 IBM Corp.
+ *
+ * This program is fre
Signed-off-by: Andrew Donnellan
Signed-off-by: Christophe Lombard
---
Looks ok to me, thanks!
[mpe: just to make sure you notice: there's a prereq patch listed under
the changelog]
Acked-by: Frederic Barrat
Changelog[v4]
- Rebase to latest upstream.
- Add new S
uint64_t desc)
It uses a new OPAL call, as the configuration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat
---
Requires skiboot patch:
http://patchwork.ozlabs.org/patch/780813/
Changelog:
- change of API
- allow disabling of p2p setting
arch/power
Le 27/06/2017 à 14:32, David Laight a écrit :
From: Frederic Barrat
Sent: 26 June 2017 19:09
P9 has support for PCI peer-to-peer, enabling a device to write in the
mmio space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new
Le 28/06/2017 à 09:22, Andrew Donnellan a écrit :
As Ian's stepping down from his maintainer role now that he's leaving IBM,
Frederic has asked me to add myself to the cxl maintainer list. Updating
accordingly.
Cc: Frederic Barrat
Cc: Ian Munsie
Signed-off-by: Andrew
-off-by: Ian Munsie
Cc: Frederic Barrat
Cc: Andrew Donnellan
Cc: linuxppc-dev@lists.ozlabs.org
---
Acked-by: Frederic Barrat
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e984645c4b0..1e8a915577fa 100644
--- a/MAINTAINERS
+++ b
Le 12/07/2017 à 17:39, Benjamin Herrenschmidt a écrit :
On Mon, 2017-06-26 at 20:08 +0200, Frederic Barrat wrote:
+ if (desc & OPAL_PCI_P2P_ENABLE) {
+ pe_init->p2p_initiator_count++;
+ } else {
+ if (pe_init->p2p_initiator
guration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat
---
Changelog:
Requires skiboot patch:
http://patchwork.ozlabs.org/patch/789763/
Changelog:
v3:
- move target reference count from skiboot to linux
v2:
- change of API
- allow disabling of p2p setting
arch
Le 22/09/2017 à 15:08, Christophe Lombard a écrit :
The a in-kernel 'library' API can be called by drivers to help
"the in-kernel library"
interaction with an IBM XSL on a POWER9 system.
The cxllib_handle_fault() API is used to handle memory fault. All memory
pages of the specified buff
ned-off-by: Christophe Lombard
Fixes: 3ced8d730063 ("cxl: Export library to support IBM XSL");
---
Thanks,
Acked-by: Frederic Barrat
Changelog[v2]
- Rebase to latest upstream.
- Change the start address of the loop.
- Rewrite the commit message.
---
drivers/misc/cxl/cxllib.c |
/card, which will provide
direct r/w access to corrosponding debug registers in the adapter
config-space.
Signed-off-by: Vaibhav Jain
---
Thanks!
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h | 1 +
drivers/misc/cxl/debugfs.c | 4
2 files changed, 5 insertions(+)
diff --git a
s patch renames the def PSL9_FIR2 to PSL9_FIR_MASK and updates
the references in the code to point to the new identifier. It also
removes the code to dump contents of FIR2 (FIR_MASK actually) in
cxl_native_irq_dump_regs_psl9().
Fixes: f24be42aab37("cxl: Add psl9 specific code")
Rep
Hi Vaibhav,
I think we can make it slightly cleaner by registering a different
callback for psl8 and psl9. The callback 'err_irq_dump_registers' is
already in place, it could just point to a different function in
psl8_ops and psl9_ops.
Fred
Le 09/10/2017 à 19:58, Vaibhav Jain a écrit :
-> As created a different function to dump the FIR register for PSL9 (Fred)
---
Thanks!
Acked-by: Frederic Barrat
drivers/misc/cxl/cxl.h| 3 ++-
drivers/misc/cxl/native.c | 15 ---
drivers/misc/cxl/pci.c| 3 ++-
3 files changed, 16 insertions(+), 5 deletions(-)
diff
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