Difference layerscape chip have not difference exit_from_l2() method.
Using function pointer for ls1028. It prepare for other layerscape
suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
ls1021a add suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 88 -
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c
b/drivers/pci/controller/dwc/pci-layerscape.c
index
ls1043a add suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 91 -
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c
b/drivers/pci/controller/dwc/pci-layerscape.c
index
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller
On Thu, Sep 21, 2023 at 07:59:51PM +0200, Christophe JAILLET wrote:
> Le 21/09/2023 à 17:37, Frank Li a écrit :
> > From: Guanhua Gao
> >
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> > Signed-off-by: Guanhua Gao
> > Signed-
On Thu, Sep 21, 2023 at 10:04:31PM +0200, Christophe JAILLET wrote:
> Le 21/09/2023 à 20:35, Frank Li a écrit :
> > On Thu, Sep 21, 2023 at 07:59:51PM +0200, Christophe JAILLET wrote:
> > > Le 21/09/2023 à 17:37, Frank Li a écrit :
> > > > From: Guanhua Gao
>
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
Notes:
change from v1 to v2
- Remove 32bit DMA mask set.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 5 +
1
On Tue, Sep 26, 2023 at 12:27:32AM -0700, Christoph Hellwig wrote:
> > + /* set 64-bit DMA mask and coherent DMA mask */
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
>
> The comment is a bit silly :)
>
> > + if (ret)
> > + return ret;
>
> Also no need to check th
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
Notes:
change from v2 to v3
- remove check return value of dma_set_mask_and_coherent. 64bit mask always
return
On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> ls1021a add suspend/resume support.
>
> Signed-off-by: Frank Li
> ---
ping
Frank
> drivers/pci/controller/dwc/pci-layerscape.c | 88 -
> 1 file changed, 87 insertions(+), 1 deletion(-)
>
&
On Wed, Sep 27, 2023 at 02:46:21PM +0200, Manivannan Sadhasivam wrote:
> On Tue, Sep 26, 2023 at 10:04:45AM -0400, Frank Li wrote:
> > From: Guanhua Gao
> >
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> > Signed-off-by: Guanhua Gao
On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
> > Signed-off-by: Frank Li
> > ---
>
> ping
>
> Frank
Ping
Frank
>
> >
On Tue, Oct 10, 2023 at 05:44:23PM +0200, Lorenzo Pieralisi wrote:
> On Tue, 26 Sep 2023 10:04:45 -0400, Frank Li wrote:
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> >
>
> Read this:
> https://lore.kernel.org/linux-pci/2
On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
> > On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> > > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > > > ls10
On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
> On Mon, Oct 16, 2023 at 10:45:25AM -0400, Frank Li wrote:
> > On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> > > On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
>
> > >
Difference layerscape chip have not difference exit_from_l2() method.
Using function pointer for ls1028. It prepare for other layerscape
suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
Change from v1 to v2
- change subject 'a' to 'A'
drivers/pc
ls1021a add suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
change from v1 to v2
- change subject 'a' to 'A'
drivers/pci/controller/dwc/pci-layerscape.c | 88 -
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/pc
ls1043a add suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
Change from v1 to v2
- Change subject 'a' to 'A'
drivers/pci/controller/dwc/pci-layerscape.c | 91 -
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/pc
On Mon, Oct 16, 2023 at 11:25:12AM -0500, Bjorn Helgaas wrote:
> On Mon, Oct 16, 2023 at 12:11:04PM -0400, Frank Li wrote:
> > On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
>
> > > Obviously Lorenzo *could* edit all your subject lines on your behal
On Mon, Oct 16, 2023 at 10:28:24PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
>
> Please add what the driver is doing during suspend/resume.
>
> > Signed-off-by: Fran
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape: Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
Since difference SoCs require different sequence for exiting L2, let's add
a separate "exit_from_l2()" callback. This callback can be used to execute
SoC specific sequence.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
- fixed according to mani's feed
ls1021a add suspend/resume support.
Implement callback ls1021a_pcie_send_turnoff_msg(), which write scfg's
SCFG_PEXPMWRCR to issue PME_Turn_off message.
Implement ls1021a_pcie_exit_from_l2() to let controller exit L2 state.
Signed-off-by: Frank Li
---
Notes:
Change from v2
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
change from v1 to v3
- new patch at v3
drivers/pci/controller/
ls1043a add suspend/resume support.
Implement ls1043a_pcie_send_turnoff_msg() to send PME_Turn_Off message.
Implement ls1043a_pcie_exit_from_l2() to exit from L2 state.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
- Remove ls_pcie_lut_readl(writel) function
Change
On Tue, Oct 17, 2023 at 03:31:41PM -0400, Frank Li wrote:
> Add suspend/resume support for ls1043 and ls1021.
> Change log see each patch
>
> Frank Li (4):
> PCI: layerscape: Add function pointer for exit_from_l2()
> PCI: layerscape: Add suspend/resume for ls1021a
> PC
On Thu, Nov 02, 2023 at 10:28:08PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:42PM -0400, Frank Li wrote:
> > Since difference SoCs require different sequence for exiting L2, let's add
> > a separate "exit_from_l2()" callback. This callback
On Thu, Nov 02, 2023 at 10:58:09PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:43PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
> > Implement callback ls1021a_pcie_send_turnoff_msg(), which write scfg's
> > SCFG
On Thu, Nov 02, 2023 at 11:03:14PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:44PM -0400, Frank Li wrote:
> > 'pf' and 'lut' is just difference name in difference chips, but basic it is
> > a MMIO base address plus an offset.
> >
On Thu, Nov 02, 2023 at 11:09:00PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:45PM -0400, Frank Li wrote:
> > ls1043a add suspend/resume support.
> > Implement ls1043a_pcie_send_turnoff_msg() to send PME_Turn_Off message.
> > Implement ls1043a_pcie_e
O Thu, Jun 15, 2023 at 12:41:11PM -0400, Frank Li wrote:
> Add support to pass Link down notification to Endpoint function driver
> so that the LINK_DOWN event can be processed by the function.
>
> Signed-off-by: Frank Li
> ---
@Lorenzo:
No comment over 1 months. Just ch
On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> From: Xiaowei Bao
>
> A workaround for the issue where the PCI Express Endpoint (EP) controller
> loses the values of the Maximum Link Width and Supported Link Speed from
> the Link Capabilities Register, which initiall
On Mon, Jul 17, 2023 at 08:45:14AM -0600, Rob Herring wrote:
> On Thu, Jun 15, 2023 at 10:41 AM Frank Li wrote:
> >
> > From: Xiaowei Bao
> >
> > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > loses the values of the Maximum Link Wi
On Mon, Jul 17, 2023 at 09:29:10PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote:
> > From: Xiaowei Bao
> >
> > A workaround for the issue where the PCI Express Endpoint (EP) controller
> > loses the values of the Maxim
Add support to pass Link down notification to Endpoint function driver
so that the LINK_DOWN event can be processed by the function.
Acked-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Change from v1 to v2
- move pci_epc_linkdown() after dev_dbg()
drivers/pci/controller/dwc/pci
event.
Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support")
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
change from v1 to v2:
- add comments at restore register
- add fixes tag
.../pci/controller/dwc/pci-layerscape-ep
Add support to pass Link down notification to Endpoint function driver
so that the LINK_DOWN event can be processed by the function.
Acked-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Change from v2 to v3
- none
Change from v1 to v2
- move pci_epc_linkdown() after dev_dbg()
drivers
event.
Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support")
Acked-by: Manivannan Sadhasivam
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
change from v2 to v3
- fix subject typo capabilities
change from v1 to v2:
- add comments at restor
On Wed, Jul 19, 2023 at 09:27:23PM +0200, Markus Elfring wrote:
> > Add support to pass …
>
> Why did you omit a cover letter for the discussed patch series once more?
Your comments is
"Will a cover letter become helpful also for the presented small patch series?"
According to my understand it
On Wed, Jul 19, 2023 at 10:08:16PM +0200, Markus Elfring wrote:
> > Cover letter just annoise people here.
>
> How do you think about advices from another information source?
>
> See also:
> https://kernelnewbies.org/PatchSeries
"You may like to include a cover letter with your patch series."
G
On Wed, Jul 19, 2023 at 11:57:07AM -0400, Frank Li wrote:
> From: Xiaowei Bao
>
> A workaround for the issue where the PCI Express Endpoint (EP) controller
> loses the values of the Maximum Link Width and Supported Link Speed from
> the Link Capabilities Register, which initiall
Add support to pass Link down notification to Endpoint function driver
so that the LINK_DOWN event can be processed by the function.
Acked-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Change from v2 to v4
- none
Change from v1 to v2
drivers/pci/controller/dwc/pci-layerscape-ep.c | 1
event.
Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support")
Acked-by: Manivannan Sadhasivam
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
change from v3 to v4
- fix wrong commit a debug code, change pr_err to pr_dbg
change from v2 to v3
- f
On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> Add support to pass Link down notification to Endpoint function driver
> so that the LINK_DOWN event can be processed by the function.
>
> Acked-by: Manivannan Sadhasivam
> Signed-off-by: Frank Li
> ---
@Lorenzo
On Mon, Jul 31, 2023 at 11:06:31AM -0400, Frank Li wrote:
> On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> > Add support to pass Link down notification to Endpoint function driver
> > so that the LINK_DOWN event can be processed by the function.
> >
>
On Wed, Aug 16, 2023 at 11:53:16AM -0400, Frank Li wrote:
> On Mon, Jul 31, 2023 at 11:06:31AM -0400, Frank Li wrote:
> > On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> > > Add support to pass Link down notification to Endpoint function driver
> > > so that
Layerscape has PME interrupt, which can be use as linkup notifer.
Set CFG_READY bit when linkup detected.
Signed-off-by: Xiaowei Bao
Signed-off-by: Frank Li
---
.../pci/controller/dwc/pci-layerscape-ep.c| 104 +-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git
Layerscape has PME interrupt, which can be used as linkup notifier.
Set CFG_READY bit when linkup detected.
Signed-off-by: Xiaowei Bao
Signed-off-by: Frank Li
---
Change from v1 to v2
- pme -> PME
- irq -> IRQ
- update dev_info message according to Bjorn's suggestion
- remove &
> -Original Message-
> From: Manivannan Sadhasivam
> Sent: Saturday, May 6, 2023 2:59 AM
> To: Frank Li
> Cc: M.H. Lian ; Mingkai Hu
> ; Roy Zang ; Lorenzo Pieralisi
> ; Rob Herring ; Krzysztof
> Wilczyński ; Bjorn Helgaas ; open
> list:PCI DRIVER FOR FR
Layerscape has PME interrupt, which can be used as linkup notifier.
Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
when linkup detected.
Signed-off-by: Xiaowei Bao
Signed-off-by: Frank Li
---
.../pci/controller/dwc/pci-layerscape-ep.c| 102 +-
1
> > > Subject: [EXT] Re: [PATCH v2 1/1] PCI: layerscape: Add the endpoint
> linkup
> > > notifier support
>
> All these quoted headers are redundant clutter since we've already
> seen them when Manivannan sent his comments. It would be nice if your
> mailer could be configured to omit them.
Our
Layerscape has PME interrupt, which can be used as linkup notifier.
Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
when linkup detected.
Signed-off-by: Xiaowei Bao
Signed-off-by: Frank Li
---
Change from v2 to v3
- align 80 column
- clear irq firstly
- dev_info to
Layerscape has PME interrupt, which can be used as linkup notifier.
Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
when linkup detected.
Acked-by: Manivannan Sadhasivam
Signed-off-by: Xiaowei Bao
Signed-off-by: Frank Li
---
Change from v3 to v4
- swap irq and
On Mon, May 15, 2023 at 11:10:49AM -0400, Frank Li wrote:
> Layerscape has PME interrupt, which can be used as linkup notifier.
> Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> when linkup detected.
>
> Acked-by: Manivannan Sadhasivam
> Signed-o
On Mon, Jun 12, 2023 at 12:12:53PM -0400, Frank Li wrote:
> On Mon, May 15, 2023 at 11:10:49AM -0400, Frank Li wrote:
> > Layerscape has PME interrupt, which can be used as linkup notifier.
> > Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex
> >
Add support to pass Link down notification to Endpoint function driver
so that the LINK_DOWN event can be processed by the function.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pci
event.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/controller/dwc/pci-layerscape
Add a API for dwc suspend/resume.
In layerscape platform call this api.
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape: Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
drivers
xit resume flow.
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedback
1. update commit message
2. move dw_pc
-by: Frank Li
---
Notes:
Change from v3 to v4
- update commit message.
- it is reset a glue logic part for PCI controller.
- use regmap_write_bits() to reduce code change.
Change from v2 to v3
- update according to mani's feedback
change from v1 to v2
- c
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
pf_lut is better than pf_* or lut* because some chip use 'pf
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. This link would then enter
L2/L3 state depending on the VAUX supply.
In the resume path, the link is brought back from L2 to L0 by doing a
software reset.
Signed-off-by: Frank Li
---
Notes:
Change
On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote:
> > In the suspend path, PME_Turn_Off message is sent to the endpoint to
> > transition the link to L2/L3_Ready state. In this SoC, there is no way to
&
On Thu, Nov 30, 2023 at 03:17:39PM -0500, Frank Li wrote:
> On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote:
> > > In the suspend path, PME_Turn_Off message is sent to the endpoint to
> >
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape(ep): Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
xit resume flow.
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- none
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedback
1. upda
.
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- update comit message
- remove a empty line
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
- pci->pp.ops = pcie->drvdata->ops,
ls_pcie_host_ops to the "ops" member of
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
pf_lut is better than pf_* or lut* because some chip use 'pf
.
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- update commit message
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
Change from v3 to v4
- Call scfg_pcie_send_turnoff_msg() shared with ls1021a
- update commit message
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape(ep): Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
xit resume flow.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v6
- none
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedba
.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v5 to v6
- remove reduntant pci->pp.ops = &ls_pcie_host_ops;
Change from v4 to v5
- update comit message
- remove a empty line
- use comments
/* Reset
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Reviewed-by: Manivannan Sadhasivam
Acked-by: Roy Zang
Signed-off-by: Frank Li
---
Notes:
pf_lut is
.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Chagne from v5 to v6
- none
Change from v4 to v5
- update commit message
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
Change from v3 to v4
On Mon, Dec 04, 2023 at 11:08:29AM -0500, Frank Li wrote:
> Add suspend/resume support for Layerscape LS1043a.
>
> In the suspend path, PME_Turn_Off message is sent to the endpoint to
> transition the link to L2/L3_Ready state. In this SoC, there is no way to
> check if the
From: Ran Wang
Enable Power Management feature on device tree, including MPC8536,
MPC8544, MPC8548, MPC8572, P1010, P1020, P1021, P1022, P2020, P2041,
P3041, T104X, T1024.
Signed-off-by: Zhao Chenhui
Signed-off-by: Ran Wang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/mpc8536si
0RDB-PB do not work because of the pcie@0 node fixup will be
overwrited by p1010si-post.dtsi file, so we move the pcie@0 node fixup
to p1010rdb-pb.dts and p1010rdb-pb_36b.dts.
Signed-off-by: Xiaowei Bao
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/p1010rdb-pb.dt
From: Li Yang
Update dts to match dts binding document.
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi | 2 +-
arch/powerpc/boot/dts
From: Li Yang
Update the node name to be align with binding document.
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/bsc9131rdb.dts| 2 +-
arch/powerpc/boot/dts/fsl/bsc9132qds.dts| 2 +-
arch/powerpc/boot/dts/fsl/c293pcie.dts | 2 +-
arch/powerpc
API in rcar_gen4_remove_dw_pcie_ep().
>
> This simplifies the DWC layer.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +
> drivers/pci/controller/dwc/pcie-designware.h| 1 -
() to make the
> purpose of this API clear. This also aligns with the DWC host driver.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++--
> drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
&g
nup() API that could be called by these
> drivers to cleanup the DWC specific resources. Currently, it just removes
> eDMA.
>
> Reported-by: Niklas Cassel
> Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
> Signed-off-by: Manivannan Sadhasivam
Review
ing
> 'core_init_notifier' flag once refclk is received from host. For the rest
> of the drivers that gets the refclk locally, this API will be called
> within dw_pcie_ep_init().
>
> Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for E
causes confusion. So,
> let's rename it to dw_pcie_ep_init_registers() to make it clear that it
> initializes the DWC specific registers.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +
On Sat, Feb 24, 2024 at 12:24:12PM +0530, Manivannan Sadhasivam wrote:
> Currently, dw_pcie_ep_init_registers() API is directly called by the glue
> drivers requiring active refclk from host. But for the other drivers, it is
> getting called implicitly by dw_pcie_ep_init(). This is due to the fact
is that, the drivers requiring refclk from host will
> send the notification once refclk is received, while others will send it
> during probe time itself.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pci-dra7xx.c
On Sat, Feb 24, 2024 at 12:24:14PM +0530, Manivannan Sadhasivam wrote:
> The PCIe link can go to LINK_DOWN state in one of the following scenarios:
>
> 1. Fundamental (PERST#)/hot/warm reset
> 2. Link transition from L2/L3 to L0
>From L0 to L2/l3
>
> In those cases, LINK_DOWN causes some non-st
On Sat, Feb 24, 2024 at 12:24:15PM +0530, Manivannan Sadhasivam wrote:
> Now that the API is available, let's make use of it. It also handles the
> reinitialization of DWC non-sticky registers in addition to sending the
> notification to EPF drivers.
>
> Signed-off-by: Manivannan Sadhasivam
> ---
On Sat, Feb 24, 2024 at 12:24:16PM +0530, Manivannan Sadhasivam wrote:
> All of the APIs are missing the Kernel-doc comments. Hence, add them.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-desig
On Tue, Feb 27, 2024 at 06:00:24PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:18:18PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:14PM +0530, Manivannan Sadhasivam wrote:
> > > The PCIe link can go to LINK_DOWN state in one of the f
On Tue, Feb 27, 2024 at 05:51:41PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:04:33PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:12PM +0530, Manivannan Sadhasivam wrote:
> > > Currently, dw_pcie_ep_init_registers() API is directly
On Tue, Feb 27, 2024 at 06:02:30PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:20:41PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:15PM +0530, Manivannan Sadhasivam wrote:
> > > Now that the API is available, let's make use of
arning message.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 7 ++-
drivers/pci/controller/dwc/pci-layerscape.c| 7 ++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/cont
> Subject: [EXT] [PATCH v2 1/1] PCI: layerscape: Add EP mode support for
> ls1028a
>
> Caution: EXT Email
>
> From: Xiaowei Bao
>
> Add PCIe EP mode support for ls1028a.
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Signed-off
> Subject: [PATCH 1/1] PCI: layerscape: Set 64-bit DMA mask
>
> From: Guanhua Gao
>
> Set DMA mask and coherent DMA mask to enable 64-bit addressing.
>
> Signed-off-by: Guanhua Gao
> Signed-off-by: Hou Zhiqiang
> Signed-off-by: Frank Li
> ---
Ping
>
d Link Speed configured by RCW.
>
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> Signed-off-by: Frank Li
> ---
Ping
> .../pci/controller/dwc/pci-layerscape-ep.c| 112 +-
> 1 file changed, 111 insertions(+), 1 deletion(-)
>
> diff -
s1028a-pcie-ep", .data = &ls1_ep_drvdata },
> { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
>
> can it be like this for better readability. ?
It is just chip name and follow name conversion, which already upstreamed and
documented.
Why do you think it not is good readability?
Frank Li
>
> Thanks,
> Alok
>
From: Xiaowei Bao
Add PCIe EP mode support for ls1028a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
Acked-by: Roy Zang
---
Change from v2 to v3
order by .compatible
Change from v2 to v2
Added
Signed-off-by: Frank Li
Acked-by: Roy Zang
All other
cie-ep", .data = &ls1_ep_drvdata },
> { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
> { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
Thanks, v3 sent.
Frank Li
>
>
>
> Thanks,
>
> Alok
> -Original Message-
> From: Frank Li
> Subject: RE: [PATCH 1/1] PCI: layerscape: Set 64-bit DMA mask
>
>
> > Subject: [PATCH 1/1] PCI: layerscape: Set 64-bit DMA mask
> >
> > From: Guanhua Gao
> >
> > Set DMA mask and coherent DMA mask to en
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