Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
-
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S | 18
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
arch/powerpc/kernel
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/include
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
arch/powerpc/include/asm/page_32.h | 17 ++---
arch/powerpc/kernel/misc_32.S | 16
arch/powerpc/kernel/ppc_ksyms_32.c | 1 -
3 files changed, 14 insertions(+), 20 deletions(-)
diff --git a
calling them
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
arch/powerpc/include/asm/cacheflush.h | 52 ++--
arch/powerpc/kernel/misc_32.S | 65 ---
arch/powerpc/kernel/ppc_ksyms.c | 2
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 insertions(+), 3 deletions
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
supported
by the MPC885 HW.
Signed-off-by: Christophe Leroy
---
arch/powerpc/sysdev/cpm1.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 5e6ff38..8ed6536 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch
for mapping IMMR
Change in v4:
* Fix of a wrong #if notified by kbuild robot in 07/23
Change in v5:
* Removed use of pmd_val() as L-value
* Adapted to match the new include files layout in Linux 4.5
Change in v6:
* Removed remaining use of pmd_val() as L-value
Christophe Leroy (23):
powerpc/8xx
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/kernel/head_8xx.S | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index e629e28..a89492e
increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy
---
v2: using bt instead of bgt and named the label explicitly
v3: no change
v4: no change
v5: removed use of pmd_val() as L-value
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: new
v4: no change
v5: no chan
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott
s at 0xfa20 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe L
will be no speculative accesses.
With this patch applied, the number of DTLB misses during the 10 min
period is reduced to 11.8 millions for a duration of 5.8s, which
represents 2% of the non-idle time hence yet another 10% reduction.
Signed-off-by: Christophe Leroy
---
v2:
- using bt instead of blt
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch
selected.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Automatic detection of available/needed memory instead of allocating 16M
for all.
v4: no change
v5: no change
v6: no change
arch/powerpc/kernel/head_8xx.S | 56 +++---
arch/powerpc/mm/8xx_mmu.c
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/mm/ini
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
v4: no change
v5: no change
v6: no change
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
arch/powerpc/mm/mmu_decl.h | 1 -
arch
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
-
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no c
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/include/asm/page_32.h | 17 ++---
arch/powerpc/kernel/misc_32.S | 16
arch/powerpc/kernel/ppc_ksyms_32.c | 1 -
3 files changed, 14 insertions(+), 20 deletions
calling them
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/include/asm/cacheflush.h | 52 ++--
arch/powerpc/kernel/misc_32.S | 65 ---
arch/powerpc/kernel/ppc_ksyms.c
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 insertions(+), 3
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel
Le 04/02/2016 12:37, Denis Kirjanov a écrit :
On 2/4/16, Christophe Leroy wrote:
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
Le 05/02/2016 08:52, Denis Kirjanov a écrit :
On 2/4/16, Christophe Leroy wrote:
Le 04/02/2016 12:37, Denis Kirjanov a écrit :
On 2/4/16, Christophe Leroy wrote:
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches
)
Change in v7:
* Don't include x_block_mapped() from compilation in
arch/powerpc/mm/fsl_booke_mmu.c when CONFIG_FSL_BOOKE is not set
(reported by kbuild test robot)
Christophe Leroy (23):
powerpc/8xx: Save r3 all the time in DTLB miss handler
powerpc/8xx: Map linear kernel RAM with 8M pages
po
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/head_8xx.S | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index e629e28
increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy
---
v2: using bt instead of bgt and named the label explicitly
v3: no change
v4: no change
v5: removed use of pmd_val() as L-value
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: new
v4: no change
v5: no chan
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott
s at 0xfa20 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe L
will be no speculative accesses.
With this patch applied, the number of DTLB misses during the 10 min
period is reduced to 11.8 millions for a duration of 5.8s, which
represents 2% of the non-idle time hence yet another 10% reduction.
Signed-off-by: Christophe Leroy
---
v2:
- using bt instead of blt
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc
selected.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Automatic detection of available/needed memory instead of allocating 16M
for all.
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/head_8xx.S | 56 +++---
arch/powerpc
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
arch/powerpc/mm/mmu_decl.h
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
-
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no c
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff
calling them
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/cacheflush.h | 52 ++--
arch/powerpc/kernel/misc_32.S | 65 ---
arch/powerpc/kernel
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/include/asm/page_32.h | 17 ++---
arch/powerpc/kernel/misc_32.S | 16
arch/powerpc/kernel/ppc_ksyms_32.c | 1 -
3 files changed, 14 insertions
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v7: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch
Le 09/02/2016 11:23, Christophe Leroy a écrit :
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
Change in v7:
* Don't include x_block_mapped()
)
Change in v7:
* No change (commit error)
Change in v8:
* Don't include x_block_mapped() from compilation in
arch/powerpc/mm/fsl_booke_mmu.c when CONFIG_FSL_BOOKE is not set
(reported by kbuild test robot)
Christophe Leroy (23):
powerpc/8xx: Save r3 all the time in DTLB miss handler
powerp
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/head_8xx.S | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index e629e28
increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy
---
v2: using bt instead of bgt and named the label explicitly
v3: no change
v4: no change
v5: removed use of pmd_val() as L-value
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: new
v4: no change
v5: no chan
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott
will be no speculative accesses.
With this patch applied, the number of DTLB misses during the 10 min
period is reduced to 11.8 millions for a duration of 5.8s, which
represents 2% of the non-idle time hence yet another 10% reduction.
Signed-off-by: Christophe Leroy
---
v2:
- using bt instead of blt
selected.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Automatic detection of available/needed memory instead of allocating 16M
for all.
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/head_8xx.S | 56 +++---
arch/powerpc
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/nohash/32/pgtable.h | 2 +-
arch/powerpc/mm/mmu_decl.h
s at 0xfa20 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe L
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
-
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no c
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff
: Christophe Leroy
---
v2: no change
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/page_32.h | 17 ++---
arch/powerpc/kernel/misc_32.S | 16
arch/powerpc/kernel/ppc_ksyms_32.c | 1 -
3 files changed, 14 insertions
calling them
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/include/asm/cacheflush.h | 52 ++--
arch/powerpc/kernel/misc_32.S | 65 ---
arch/powerpc/kernel
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
v4: no change
v5: no change
v6: no change
v8: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch
368b78
[0.00] ---[ end trace dc8fa200cb88537f ]---
Signed-off-by: Christophe Leroy
---
This patch goes on top of the following serie:
[PATCH v8 00/23] powerpc/8xx: Use large pages for RAM and IMMR and other
improvments
arch/powerpc/mm/pgtable_32.c | 5 +++--
1 file changed, 3 insertions(+), 2 del
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
Le 14/02/2016 21:40, Denis Kirjanov a écrit :
On 2/11/16, Christophe Leroy wrote:
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
PPC32 doesn't have the PACA structure, so we use the task_info
structure to store the accounting data.
In order to reuse on PPC32 the PPC64 func
n PPC32 and
u64 on PPC64
Signed-off-by: Christophe Leroy
---
Changes in v3: unlike previous version of the patch that was inspired
from IA64 architecture, this new version tries to reuse as much as
possible the PPC64 implementation.
PPC32 doesn't have PACA and past discusion on v2 version
prom_init is
in __init section, it is freed after boot anyway.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/prom_init.c| 213 ++---
arch/powerpc/kernel/prom_init_check.sh | 2 +-
2 files changed, 173 insertions(+), 42 deletions(-)
diff --git a/arch
appers,
we therefore have to fallback to the generic versions when
KASAN is active, otherwise KASAN checks will be skipped.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/kasan.h | 15 +++
arch/powerpc/include/asm/string.h | 32 +---
ar
In kernel/cputable.c, explicitly use memcpy() instead of *y = *x;
This will allow GCC to replace it with __memcpy() when KASAN is
selected.
Acked-by: Dmitry Vyukov
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/cputable.c | 13 ++---
1 file changed, 10 insertions(+), 3
In preparation of KASAN, move early_init() into a separate
file in order to allow deactivation of KASAN for that function.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/Makefile | 2 +-
arch/powerpc/kernel/early_32.c | 38 ++
arch/powerpc/kernel
.h in
asm/pgtable-types.h
==> might be fixed independently but not needed for this serie.
Christophe Leroy (11):
powerpc/32: Move early_init() in a separate file
powerpc: prepare string/mem functions for KASAN
powerpc/prom_init: don't use string functions from lib/
powerpc/
Since commit 400c47d81ca38 ("powerpc32: memset: only use dcbz once cache is
enabled"), memset() can be used before activation of the cache,
so no need to use memset_io() for zeroing the BSS.
Acked-by: Dmitry Vyukov
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/earl
in a previous patch.
An early mapping is set as soon as the kernel code has been
relocated at its definitive place.
Then the definitive mapping is set once paging is initialised.
For modules, the shadow area is allocated at module_alloc().
Signed-off-by: Christophe Leroy
---
arch/powerpc
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