On Sat, 11 Jan 2014 12:06:32 Benjamin Herrenschmidt wrote:
> On Fri, 2014-01-10 at 16:52 -0800, Greg KH wrote:
> > > >Signed-off-by: Alistair Popple
> > > >Acked-by: Alan Stern
> > > >Cc: linux-...@vger.kernel.org
> > > >
> > >
On Wed, 29 Jan 2014 07:19:55 Benjamin Herrenschmidt wrote:
> On Tue, 2014-01-28 at 16:03 +0100, Olaf Hering wrote:
> > d084775738b746648d4102337163a04534a02982 is the first bad commit
> > commit d084775738b746648d4102337163a04534a02982
> > Author: Alistair Popple
> >
updated.
This commit initialises the it_page_shift field to 4K for the DART
iommu.
Signed-off-by: Alistair Popple
---
arch/powerpc/sysdev/dart_iommu.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index bd968a4..62c47bb
The IBM Akebono board is a development board for the new PPC476GTR
system on chip (SoC).
This is just a resubmission of the previous patches rebased on kernel
v3.13. Ben H has indicated the subsystem specific changes should be
merged via the appropriate kernel trees.
Alistair Popple (7):
IBM
This patch adds a SDHCI platform driver for the new IBM PPC476GTR SoC
which is on the Akebono board.
Signed-off-by: Alistair Popple
---
drivers/mmc/host/Kconfig | 12
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/sdhci-of-476gtr.c | 60
reasonable defaults if no platform data is present. This is
similar to what is currently done in ehci-platform.c.
Signed-off-by: Alistair Popple
Acked-by: Alan Stern
---
drivers/usb/host/ohci-platform.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers
.
Signed-off-by: Alistair Popple
Acked-by: Benjamin Herrenschmidt
Cc: "David S. Miller"
---
.../devicetree/bindings/powerpc/4xx/emac.txt |9 +
drivers/net/ethernet/ibm/emac/Kconfig |4 +
drivers/net/ethernet/ibm/emac/Makefile |1 +
drivers/net/et
iver is removed and the 440EPX
specific quirks are added to the ehci-platform driver.
Signed-off-by: Alistair Popple
---
drivers/usb/host/Kconfig |7 +-
drivers/usb/host/ehci-hcd.c |5 -
drivers/usb/host/ehci-platform.c | 87 +-
drivers/u
.
Signed-off-by: Alistair Popple
---
arch/powerpc/platforms/44x/Makefile|2 +-
arch/powerpc/platforms/44x/currituck.c | 233
arch/powerpc/platforms/44x/ppc476.c| 233
3 files changed, 234 insertions(+), 234 deletions
allow PCI devices write access to the HSTA module.
Signed-off-by: Alistair Popple
---
arch/powerpc/boot/dts/akebono.dts | 46 +--
arch/powerpc/boot/treeboot-akebono.c | 15 ---
arch/powerpc/platforms/44x/Kconfig|2 +
arch/powerpc/sysdev/Kconfig |6 +
arch/powerpc
This patch adds support for the IBM Akebono board.
Signed-off-by: Alistair Popple
---
.../devicetree/bindings/powerpc/4xx/akebono.txt| 54 +++
arch/powerpc/boot/Makefile |3 +
arch/powerpc/boot/dcr.h|4 +
arch/powerpc/boot/dts
On Fri, 21 Feb 2014 15:16:52 Arnd Bergmann wrote:
> On Friday 21 February 2014 17:31:29 Alistair Popple wrote:
> > +static const struct of_device_id ohci_of_match[] = {
> > + { .compatible = "usb-ohci", },
> > + {},
> > +};
> > +
>
On Fri, 21 Feb 2014 10:41:50 Alan Stern wrote:
> On Fri, 21 Feb 2014, Alistair Popple wrote:
> > Currently the ppc-of driver uses the compatibility string
> > "usb-ehci". This means platforms that use device-tree and implement an
> > EHCI compatible interface have
On Fri, 21 Feb 2014 15:14:30 Arnd Bergmann wrote:
> On Friday 21 February 2014 17:31:27 Alistair Popple wrote:
> > +config MMC_SDHCI_OF_476GTR
> > + tristate "SDHCI OF support for the IBM PPC476GTR SoC"
> > + depends on MMC_SDHCI_PLTFM
> > + depends
On Fri, 21 Feb 2014 11:18:23 Mark Rutland wrote:
> On Fri, Feb 21, 2014 at 06:31:28AM +0000, Alistair Popple wrote:
[...]
>
> > + /* Check for RGMII flags */
> > + if (of_get_property(ofdev->dev.of_node, "has-mdio", NULL))
> > + d
linker options and ensures
that all module output sections are aligned to 4K page boundaries. The
work around is only required when building modules.
Signed-off-by: Alistair Popple
---
arch/powerpc/Makefile |5 +
arch/powerpc/platforms/44x/Kconfig| 14
On Mon, 24 Feb 2014 08:35:06 Josh Boyer wrote:
> On Mon, Feb 24, 2014 at 2:00 AM, Alistair Popple
wrote:
> > This patch adds an option to enable a work around for an icache bug on
> > 476 that can cause execution of stale instructions when falling
> > through pages (IBM err
On Sat, 22 Feb 2014 07:41:26 Benjamin Herrenschmidt wrote:
> On Fri, 2014-02-21 at 15:33 +0100, Arnd Bergmann wrote:
[...]
>
> Should we (provided it's possible in HW) create two ranges instead ? One
> covering RAM and one covering MSIs ? To avoid stray DMAs whacking random
> HW registers in the
The IBM Akebono board is a development board for the new PPC476GTR
system on chip (SoC).
This version of the series updates the device tree and drops the USB
patches as the equivalent functionality is already in linux-next. It
also addresses feedback from the previous submission.
Alistair Popple
This patch adds a generic platform driver registration to the exiting SDHCI
platform driver using the devicetree compatibility string "generic-sdhci".
Signed-off-by: Alistair Popple
---
.../devicetree/bindings/mmc/sdhci-pltfm.txt| 16 +
drivers/mmc/host/sdh
.
Signed-off-by: Alistair Popple
Acked-by: Benjamin Herrenschmidt
---
.../devicetree/bindings/powerpc/4xx/emac.txt | 9 +
drivers/net/ethernet/ibm/emac/Kconfig | 4 +
drivers/net/ethernet/ibm/emac/Makefile | 1 +
drivers/net/ethernet/ibm/emac/core.c
.
Signed-off-by: Alistair Popple
---
arch/powerpc/platforms/44x/Makefile| 2 +-
arch/powerpc/platforms/44x/currituck.c | 233 -
arch/powerpc/platforms/44x/ppc476.c| 233 +
3 files changed, 234 insertions(+), 234 deletions
This patch adds support for the IBM Akebono board.
Signed-off-by: Alistair Popple
---
.../devicetree/bindings/powerpc/4xx/akebono.txt| 54 +++
arch/powerpc/boot/Makefile | 3 +
arch/powerpc/boot/dcr.h| 4 +
arch/powerpc/boot/dts
allow PCI devices write access to the HSTA module.
Signed-off-by: Alistair Popple
---
.../devicetree/bindings/powerpc/4xx/hsta.txt | 19 ++
arch/powerpc/boot/dts/akebono.dts | 46 -
arch/powerpc/boot/treeboot-akebono.c | 15 --
arch/powerpc/platforms/44x
.
Signed-off-by: Alistair Popple
Acked-by: Benjamin Herrenschmidt
---
This version just fixes the coding style as suggested by David M.
.../devicetree/bindings/powerpc/4xx/emac.txt | 9 +
drivers/net/ethernet/ibm/emac/Kconfig | 4 +
drivers/net/ethernet/ibm/emac/Makefile
apm821xx_pciex_init_port_hw.
Signed-off-by: Alistair Popple
---
arch/powerpc/sysdev/ppc4xx_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 64603a1..4914fd3 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch
de and renames it.
>
> Since pnv_npu_tce_invalidate() does really invalidate the entire cache,
> this uses pnv_pci_ioda2_tce_invalidate_entire() directly for NPU.
> This adds an explicit comment for workaround for invalidating NPU TCE
> cache.
>
> Signed-off-by: Alexey Kardas
define and use iommu_table_group_ops.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Alistair Popple
> ---
> arch/powerpc/platforms/powernv/npu-dma.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/n
propagate DMA/TCE changes the other way (NVLink
device to PCI device) as well, but it proved unnecessary and unused. This
patch cleans up the last bit of that behaviour and looks good to me as well.
> Reviewed-by: David Gibson
Reviewed-by: Alistair Popple
>
>
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
nvalidation after changing TVT.
Good idea, even though I guess we're unlikely to hit a problem in practice as
I'm pretty sure on a normal system the links would get retrained between runs
with different TVTs which implies the NPU gets reset too.
> Signed-off-by: Alexey Kardashevskiy
Hi Gavin,
> >Why exactly cannot EEH reset changes go to a smaller separate patchset
> >(before hotplug)?
> >
>
> As I explained before, the patchset's order is: PCI generic part,
> PowerNV PCI related, EEH related, device-tree part and hotplug driver.
>
> The EEH reset change is included in PA
Hi Gavin,
I was reading through this to understand how it all works and noticed a couple
of things, comments below.
- Alistair
On Wed, 17 Feb 2016 14:44:28 Gavin Shan wrote:
> +
> +static void pnv_php_handle_poweron(struct pnv_php_slot *php_slot)
> +{
> + void *fdt, *fdt1, *dt;
> + in
Hi David,
On Fri, 15 Apr 2016 14:40:20 David Gibson wrote:
> On Tue, Apr 12, 2016 at 06:37:50PM +1000, Alexey Kardashevskiy wrote:
> > IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
> > also has a couple of fast speed links (NVLink). The interface to links
> > is exposed as a
On Tue, 19 Apr 2016 20:36:48 Alexey Kardashevskiy wrote:
> On 02/17/2016 02:44 PM, Gavin Shan wrote:
> > This adds standalone driver to support PCI hotplug for PowerPC PowerNV
> > platform that runs on top of skiboot firmware. The firmware identifies
> > hotpluggable slots and marked their device t
On Wed, 20 Apr 2016 14:14:13 Alexey Kardashevskiy wrote:
> >
> >>
> >> btw how will new OPAL react if old kernel is running, i.e. not passing
> >> @state
> >> at all? If it is initialized to NULL somewher - fine but what exactly does
> >> this initialization and makes sure that OPAL won't see g
this
patch series. Instead the links are treated as standard PCIe devices
sitting under a Nvlink specific PHB type. This allows existing kernel
interfaces to be used for the management and control of the links.
Alistair Popple (2):
Revert "powerpc/pci: Remove unused struct pci_dn.pc
This commit removed the pcidev field from struct pci_dn as it was no
longer in use by the kernel. However to support finding the
association of Nvlink devices to GPU devices from the device-tree this
field is required.
This reverts commit 250c7b277c65.
Signed-off-by: Alistair Popple
---
arch
. Therefore all DMA operations are setup and
controlled via the PCIe device.
EEH is not presently supported for the NPU devices, although it may be
added in future.
Signed-off-by: Alistair Popple
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/pci.h| 4 +
arch/powerpc
. Therefore all DMA operations are setup and
controlled via the PCIe device.
EEH is not presently supported for the NPU devices, although it may be
added in future.
Signed-off-by: Alistair Popple
Signed-off-by: Gavin Shan
---
This patch includes the following changes from v1:
- Minor variable
OPAL event delivery being delayed or dropped
on some systems.
The bug is fixed by calling opal_handle_events(...) instead of
duplicating code in opal_event_unmask(...).
Signed-off-by: Alistair Popple
Reported-by: Douglas L Lehr
Cc: sta...@vger.kernel.org
---
arch/powerpc/platforms/powernv
On Tue, 8 Dec 2015 09:10:19 Michael Ellerman wrote:
> Subject should start "powerpc/", so probably "powerpc/opal-irqchip:", I can
> fix
> it up here.
Ok, thanks.
> On Mon, 2015-07-12 at 00:28:28 UTC, Alistair Popple wrote:
> > The OPAL event calls return a
ret_from_syscall+0x0/0x3c
--- Exception: c01 (System Call) at b77b69f4
SP (bfc4a670) is in userspace
0:mon>
Signed-off-by: Alistair Popple
Reported-by: Ivan Mikhaylov
---
arch/powerpc/kernel/misc_32.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/ker
Thanks for the review Michael. I'll do a respin to address the comments below.
On Mon, 14 Dec 2015 20:26:27 Michael Ellerman wrote:
> Hi Alistair,
>
> Just a few nitty things ...
>
> On Tue, 2015-10-11 at 02:28:11 UTC, Alistair Popple wrote:
> > NV-Link is a high speed
this
patch series. Instead the links are treated as standard PCIe devices
sitting under a NVLink specific PHB type. This allows existing kernel
interfaces to be used for the management and control of the links.
Alistair Popple (3):
Revert "powerpc/pci: Remove unused struct pci_dn.pc
truct
pci_dn.pcidev field").
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/pci-bridge.h | 1 +
arch/powerpc/platforms/powernv/pci-ioda.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/powerpc/include/asm/pci-bridge.h
index 37fc53
. Therefore all DMA operations are setup and controlled via
the PCIe device.
EEH is not presently supported for the NPU devices, although it may be
added in future.
Signed-off-by: Alistair Popple
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/pci.h| 4 +
arch/powerpc/platforms
Move __raw_rw_writeq() from platforms/powernv/pci-ioda.c to
include/asm/io.h so that it can be used by other code.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/io.h | 11 +++
arch/powerpc/platforms/powernv/pci-ioda.c | 10 --
2 files changed, 11
problem by queuing the work if an event is
active during unmasking, which is similar to the pre-endian fix
behaviour.
Signed-off-by: Alistair Popple
Reported-by: Andrew Donnellan
Cc: sta...@vger.kernel.org
---
Michael,
I'm quite confident this fixes the problem as it is just reverting
peer
PEs are updated.
Signed-off-by: Alistair Popple
---
arch/powerpc/platforms/powernv/pci-ioda.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 323e1e5..458133f 100644
--- a
assignment for NPU devices such that NPU
devices which connect to the same GPU are assigned to the same
PE#.
Signed-off-by: Alistair Popple
---
arch/powerpc/platforms/powernv/pci-ioda.c | 73 ---
1 file changed, 66 insertions(+), 7 deletions(-)
diff --git a/arch
P8+ hardware reports all errors on PE#0. This patch ensures PE#0 is
not assigned to NPU devices so that it can be used for EEH.
Signed-off-by: Alistair Popple
---
arch/powerpc/platforms/powernv/pci-ioda.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc
> But hmm, the dt_cpu_ftrs parsing should be picking those up and setting
> them by default I would think (or maybe not because you don't expect
> FSCR bit if OS support is not required).
Right - the generic dt_cpu_ftrs didn't do the FSCR enablement which I assume
is because if OS support is requ
for prefixed
> instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
>
> Signed-off-by: Jordan Niethe
Confirmed the definitions here match the specifications so:
Reviewed-by: Alistair Popple
> ---
> v2: Combined all the commits concerning SRR1 bits.
> -
> @@ -487,12 +487,13 @@ int kprobe_post_handler(struct pt_regs *regs)
> {
> struct kprobe *cur = kprobe_running();
> struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
> + int len = ppc_inst_len(ppc_inst_read(cur->ainsn.insn));
I am no kprobes expert but it seems based on the code
Two new future architectural features requiring HWCAP bits are being
developed. Once allocated in the kernel firmware can enable these via
device tree cpu features.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/uapi/asm/cputable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a
On Wednesday, 1 April 2020 9:47:03 AM AEDT Michael Neuling wrote:
> On Tue, 2020-03-31 at 12:12 -0300, Tulio Magno Quites Machado Filho wrote:
> > Alistair Popple writes:
> > > diff --git a/arch/powerpc/include/uapi/asm/cputable.h
> > > b/arch/powerpc/include/uapi
Two new future architectural features requiring HWCAP bits are being
developed. Once allocated in the kernel firmware can enable these via
device tree cpu features.
Signed-off-by: Alistair Popple
---
v2: ISA v3.10 -> ISA v3.1
---
arch/powerpc/include/uapi/asm/cputable.h | 2 ++
1 file chan
On Thursday, 2 April 2020 10:52:37 AM AEDT Jordan Niethe wrote:
> On Wed, Apr 1, 2020 at 9:32 PM Balamuruhan S wrote:
> > On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> > > Currently unsigned ints are used to represent instructions on powerpc.
> > > This has worked well as instructions
-off-by: Alistair Popple
---
arch/powerpc/include/asm/cputable.h | 1 +
arch/powerpc/include/asm/reg.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 86efd5eb0389..5cd111c63b5a 100644
Enable Advertising support for cpu feature ISA v3.1 if advertised in the
device-tree.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index
> diff --git a/arch/powerpc/include/asm/inst.h
> b/arch/powerpc/include/asm/inst.h index 70b37a35a91a..7e23e7146c66 100644
> --- a/arch/powerpc/include/asm/inst.h
> +++ b/arch/powerpc/include/asm/inst.h
> @@ -8,23 +8,67 @@
>
> struct ppc_inst {
> u32 val;
> +#ifdef __powerpc64__
> +
On Wednesday, 13 November 2019 4:38:21 AM AEDT Frederic Barrat wrote:
>
> Le 27/09/2019 à 08:54, Alexey Kardashevskiy a écrit :
> >
> >
> > On 27/09/2019 03:15, Frederic Barrat wrote:
> >>
> >>
> >> Le 26/09/2019 à 18:44, Andrew Donnellan a écrit :
> >>> On 9/9/19 5:45 pm, Frederic Barrat wrote:
On Monday, 18 November 2019 12:24:24 PM AEDT Oliver O'Halloran wrote:
> On Mon, Nov 18, 2019 at 12:06 PM Alistair Popple
wrote:
> >
> > On Wednesday, 13 November 2019 4:38:21 AM AEDT Frederic Barrat wrote:
> > >
> > > However, one question is whether
On Monday, 2 December 2019 12:59:49 PM AEDT Alexey Kardashevskiy wrote:
> Here is an attempt to support bigger DMA space for devices
> supporting DMA masks less than 59 bits (GPUs come into mind
> first). POWER9 PHBs have an option to map 2 windows at 0
> and select a windows based on DMA address b
On Monday, 6 April 2020 8:42:57 PM AEST Jordan Niethe wrote:
> On Mon, 6 Apr 2020, 7:52 pm Alistair Popple, wrote:
> > > diff --git a/arch/powerpc/include/asm/inst.h
> > > b/arch/powerpc/include/asm/inst.h index 70b37a35a91a..7e23e7146c66
> > > 100644
> > >
On Saturday, 4 April 2020 2:32:08 AM AEST Segher Boessenkool wrote:
> Hi!
>
> On Fri, Apr 03, 2020 at 03:10:54PM +1100, Alistair Popple wrote:
> > +#define PCR_ARCH_300 0x10/* Architecture 3.00 */
>
> It's called 3.0, not 3.00?
Thanks. I&#
On Tuesday, 21 April 2020 11:30:52 AM AEST Alistair Popple wrote:
> On Saturday, 4 April 2020 2:32:08 AM AEST Segher Boessenkool wrote:
> > Hi!
> >
> > On Fri, Apr 03, 2020 at 03:10:54PM +1100, Alistair Popple wrote:
> > > +#define PCR_ARCH_300 0x10
MMA (matrix multiply accumulate) instructions are only permitted to
execute when enabled via a PCR bit. Enable this bit when support is
advertised by a CPU device tree feature.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/dt_cpu_ftrs.c | 17
state is updated to match FSCR after feature
detection is complete.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 36bc0d5c4f3a..dede8f0b678f
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
There seems to be a minor typo which breaks compilation when
CONFIG_MPROFILE_KERNEL is not enabled. See the fix below.
---
arch/powerpc/kernel/trace/ftrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/
ftrace
Hi Jordan,
I needed the below fix for building with CONFIG_STRICT_KERNEL_RWX enabled.
Hopefully it's correct, I have not yet had a chance to test it beyond building
it.
- Alistair
---
arch/powerpc/lib/code-patching.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
nd instance. Arguably the
argument type could be changed to an unsigned long but then we'd just end up
with more casts so this is ok to me at least.
Reviewed-by: Alistair Popple
of(unsigned int) * 2)
> +#define BPT_WORDS (BPT_SIZE / sizeof(unsigned int))
Minor nit-pick but IMHO this would be more logical if you defined BPT_WORDS
first like so:
#define BPT_WORDS (2)
#define BPT_SIZE (sizeof(unsigned int) * BPT_WORDS)
Otherwise this l
I probably would have just folded this change into patch 2 but it looks fine to
me.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:41:56 PM AEST Jordan Niethe wrote:
> A modulo operation is used for calculating the current offset from a
> breakpoint within the breakpoint tab
ience trying to build this
series suggests that assumption is reasonably accurate :-)
Michael - this requires a minor fix up when merged on top of Ravi's 2nd DAWR
series, let me know if you need it.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:41:58 PM AEST Jordan Niethe wrote:
Looks good to me in that it doesn't look to change the behaviour of any
existing code.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:00 PM AEST Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '&g
I'm not a uprobe expert so I don't follow why we need this read here but the
rest of the patch looked ok in that it shouldn't change behaviour (and in
practice neither should the above) so:
Reviewed-by: Alistair Popple
> if (ret > 0)
> return true;
>
Looks good.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:05 PM AEST Jordan Niethe wrote:
> Introduce a probe_user_read_inst() function to use in cases where
> probe_user_read() is used for getting an instruction. This will be more
> useful for prefixed instructions.
>
valid (ie. crossing a 64 byte boundary) prefix instruction sequence.
In practice this doesn't seem like it would cause any real issues and the rest
of the patch does not appear to change any existing behaviour.
Reviewed-by: Alistair Popple
>
> if (!expected_nop
Without CONFIG_STRICT_KERNEL_RWX this boils down to doing the same thing
(although with a few more safety checks along the way), and with
CONFIG_STRICT_KERNEL_RWX this should make it actually work (although perhaps
there was some other mechanism that made it work anyway).
Reviewed-by: Alistair
Doesn't change any behaviour from what I can see.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:08 PM AEST Jordan Niethe wrote:
> Define specific __get_user_instr() and __get_user_instr_inatomic()
> macros for reading instructions from user space.
>
> Signed-off-
Looks good,
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:09 PM AEST Jordan Niethe wrote:
> Currently all instructions have the same length, but in preparation for
> prefixed instructions introduce a function for returning instruction
> length.
>
> Signed-off-by
Shouldn't change anything and will be correct once prefix instructions are
defined.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:10 PM AEST Jordan Niethe wrote:
> Currently in xmon, mread() is used for reading instructions. In
> preparation for prefixed instructions, cre
I can't see any side-effects from patching both instructions at the same time.
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:11 PM AEST Jordan Niethe wrote:
> When a new breakpoint is created, the second instruction of that
> breakpoint is patched with a trap instruction. T
I guess this could change if there were prefixed branch instructions, but there
aren't so:
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:12 PM AEST Jordan Niethe wrote:
> test_translate_branch() uses two pointers to instructions within a
> buffer, p and q, to test patch_br
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:14 PM AEST Jordan Niethe wrote:
> Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
> exception is a prefixed instruction that crosses a 64-byte boundary.
> Add the PREFIXED SRR1 bit definition for exceptions
When reviewing earlier patches in this series I assumed the data type would
eventually change size (on PPC64 at least) so I was looking for any possible
side effects this may cause, but I didn't notice any so I think this should be
ok:
Reviewed-by: Alistair Popple
However I haven&
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:16 PM AEST Jordan Niethe wrote:
> Expand the code-patching self-tests to includes tests for patching
> prefixed instructions.
>
> Signed-off-by: Jordan Niethe
> ---
> v6: New to series
> ---
> arch/powerpc/lib/M
Hmm, I was hoping to add a tested by but I'm seeing the following failure in
Mambo:
[1.475459] feature-fixups: test failed at line 730
Based on the name of the test it looks like you probably made a copy/paste
error in ftr_fixup_prefix2_expected. I suspect you probably meant to use the
alt
Reviewed-by: Alistair Popple
On Friday, 1 May 2020 1:42:18 PM AEST Jordan Niethe wrote:
> If a prefixed instruction results in an alignment exception, the
> SRR1_PREFIXED bit is set. The handler attempts to emulate the
> responsible instruction and then increment the NIP pas
I am still slowly wrapping my head around XIVE and it's interaction with KVM
but from what I can see this looks good and is needed so we can enable
StoreEOI support in future so:
Reviewed-by: Alistair Popple
On Thursday, 20 February 2020 7:15:06 PM AEST Cédric Le Goater wrote:
>
On Saturday, 9 May 2020 5:58:57 PM AEST Nicholas Piggin wrote:
> Excerpts from Paul Mackerras's message of May 9, 2020 3:02 pm:
> > Microwatt is a FPGA-based implementation of the Power ISA. It
> > currently only implements little-endian 64-bit mode, and does
> > not (yet) support SMP.
> >
> > Th
Two new future architectural features requiring HWCAP bits are being
developed. Once allocated in the kernel firmware can enable these via
device tree cpu features.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/uapi/asm/cputable.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a
This series brings together three previously posted patches required for
POWER10 support and introduces a new patch enabling POWER10 architected
mode.
Alistair Popple (4):
powerpc: Add new HWCAP bits
powerpc: Add base support for ISA v3.1
powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1
-off-by: Alistair Popple
---
arch/powerpc/include/asm/cputable.h | 1 +
arch/powerpc/include/asm/reg.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 40a4d3c6fd99..36f894dea9e7 100644
Enable Advertising support for cpu feature ISA v3.1 if advertised in the
device-tree.
Signed-off-by: Alistair Popple
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index
PVR value of 0x0F06 means we are arch v3.10 compliant (i.e. POWER10).
Signed-off-by: Cédric Le Goater
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/cputable.h | 16 ++--
arch/powerpc/include/asm/mmu.h| 1 +
arch/powerpc/include/asm/prom.h | 1
On Friday, 10 August 2018 5:07:56 PM AEST Michael Ellerman wrote:
> Reza Arbab writes:
> > From: Alistair Popple
> >
> > Some device drivers support out of order access to GPU memory. This does
> > not affect the CPU view of memory but it does affect the GPU vie
Thanks Mark,
Looks like some worthwhile improvments to be had. I've added a couple of
comments inline below.
> +#define PAGE_64K (64UL * 1024) +#define PAGE_2M (2UL * 1024 * 1024) +#define
> PAGE_1G (1UL * 1024 * 1024 * 1024)
include/linux/sizes.h includes definitions for SZ_64K, SZ_2M, SZ_1G, e
101 - 200 of 740 matches
Mail list logo
