Hello,
For the e500 processors, it appears that the first 3 of 16 permanent
TLB entries are used to map lowmem. Are the other 13 ever used?
Thanks,
-Aaron
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evalidate_and_attach: ENTER
> ata_eh_recover: EXIT, rc=0
> ata_scsi_error: EXIT
The above sequence of ATA calls you are seeing is essentially
identical to what I ran into -- part of the registration attempted to
either enable interrupts or soft reset the card, the er
e, but I was hoping that this problem had already been seen and
addressed and could be handled with the right text in the DTS file.
Thanks,
Aaron Pace
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e7e9cf8d0a8b374a48aa94]
I didn't have time to delve into the whys & hows, but this commit
caused the same issue on an 8572 platform.
Reverting this one change allows everything (including 36-bit memory
access) to work correctly, as before.
-Aaron Pace
_
>
> Is a simple "hello world" module sufficient to show the issue? I'll look
> into it this week.
>
> - k
It wasn't in my situation, unfortunately. To duplicate this, I had
one relatively large kernel module, and then one simple 'hello world'
module that did nothing more than call an exported f
Hello,
I wrote to this list quite some time ago concerning a board that has 2
gigs of ram mapped in at 0x0.. - 0x0.7fff., and a second 2
gigs of ram at 0x1.. - 0x1.7fff.. Kumar responded and
mentioned that this wasn't currently supported in the powerpc
architecture. I've
On Thu, Jul 2, 2009 at 3:14 PM, Scott Wood wrote:
> Aaron Pace wrote:
>>
>> In MMU_init of arch/powerpc/mm/init_32.c, where the current code sets
>> lmb.memory.cnt to zero, I instead walk through the memory regions and
>> call lmb_reserve for each chunk of memory that
Hello,
I'm working on a design using a Freescale MPC8572 processor.
We are using 4 gigs of memory, and also need a window of 512 megs for
PCI-E devices.
What I have done is set up the first 2G of memory from 0x0 - 0x7f, the
PCI windows from 0x8 - 0x9f, localbus devices + CCSRBAR from 0xf -
0xf
>
> Its possible in that Linux supports this. However the PPC32 code does not
> exist and would need to be added to support non-contiguous memory ranges.
>
> What exact PCI-E needs do you have? Is PCI-E performance critical? Is
> (are) your pci device(s) 64-bit address capable?
>
> I ask because
