From: Valentin Schneider
The scheduler currently expects NUMA node distances to be stable from
init onwards, and as a consequence builds the related data structures
once-and-for-all at init (see sched_init_numa()).
Unfortunately, on some architectures node distance is unreliable for
offline node
Fabiano Rosas writes:
> Michael Ellerman writes:
>
> Hi, I already mentioned these things in private, but I'll post here so
> everyone can see:
>
>> Because pte_update() takes the set of PTE bits to set and clear we can't
>> use our existing helpers, eg. pte_wrprotect() etc. and instead have to
>
Use L1_CACHE_BYTES as the dma alignment size, use 'sizeof(long)'
is wrong.
Signed-off-by: Xianting Tian
Reviewed-by: Shile Zhang
---
drivers/tty/hvc/hvc_console.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
in
Dear all,
This patch series make hvc framework pass DMA capable memory to
put_chars() of hvc backend(eg, virtio-console), and revert commit
c4baad5029 ("virtio-console: avoid DMA from stack”)
V1
virtio-console: avoid DMA from vmalloc area
https://lkml.org/lkml/2021/7/27/494
For v1 patch, Arnd Be
As well known, hvc backend driver(eg, virtio-console) can register its
operations to hvc framework. The operations can contain put_chars(),
get_chars() and so on.
Some hvc backend may do dma in its operations. eg, put_chars() of
virtio-console. But in the code of hvc framework, it may pass DMA
inc
This revert commit c4baad5029 ("virtio-console: avoid DMA from stack")
hvc framework will never pass stack memory to the put_chars() function,
So the calling of kmemdup() is unnecessary, we can remove it.
Signed-off-by: Xianting Tian
Reviewed-by: Shile Zhang
---
drivers/char/virtio_console.c |
No need to re-read SPRN_THREAD, we can calculate thread address
from current (r2).
And remove a reload of value 1 into r4 as r4 is already 1.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/fpu.S| 3 +--
arch/powerpc/kernel/vector.S | 4 +---
2 files changed, 2 insertions(+), 5 dele
Hi Xianting,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on char-misc/char-misc-testing soc/for-next v5.14-rc6
next-20210818]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
Hi Martin,
Use scsi_cmd_to_rq(scsi_cmnd)->tag in preference to scsi_cmnd.tag.
Applied to 5.15/scsi-staging and rebased for bisectability.
Thanks, and sorry for the hassle. But I would still like the maintainers
to have a look, as I was curious about current usage of scsi_cmnd.tag in
tha
Excerpts from Madhavan Srinivasan's message of August 17, 2021 11:06 pm:
>
> On 8/16/21 12:59 PM, Nicholas Piggin wrote:
>> Interrupt handling code would like to know whether perf is enabled, to
>> know whether it should enable MSR[EE] to improve PMI coverage.
>>
>> Cc: Madhavan Srinivasan
>> Cc:
Laurent reported that STRICT_MODULE_RWX was causing intermittent crashes
on one of his systems:
kernel tried to execute exec-protected page (c00804073278) - exploit
attempt? (uid: 0)
BUG: Unable to handle kernel instruction fetch
Faulting instruction address: 0xc00804073278
Oops:
Le 18/08/2021 à 14:05, Michael Ellerman a écrit :
Laurent reported that STRICT_MODULE_RWX was causing intermittent crashes
on one of his systems:
kernel tried to execute exec-protected page (c00804073278) - exploit
attempt? (uid: 0)
BUG: Unable to handle kernel instruction fetch
> On 18-Aug-2021, at 5:11 PM, Nicholas Piggin wrote:
>
> Excerpts from Madhavan Srinivasan's message of August 17, 2021 11:06 pm:
>>
>> On 8/16/21 12:59 PM, Nicholas Piggin wrote:
>>> Interrupt handling code would like to know whether perf is enabled, to
>>> know whether it should enable MSR[
Minor optimization in the 'perf_instruction_pointer' function code by
making use of stack siar instead of mfspr.
Fixes: 75382aa72f06 ("powerpc/perf: Move code to select SIAR or pt_regs
into perf_read_regs")
Signed-off-by: Kajol Jain
---
arch/powerpc/perf/core-book3s.c | 2 +-
1 file changed, 1 i
Drop the case of returning 0 as instruction pointer since kernel
never executes at 0 and userspace almost never does either.
Fixes: e6878835ac47 ("powerpc/perf: Sample only if SIAR-Valid
bit is set in P7+")
Signed-off-by: Kajol Jain
---
arch/powerpc/perf/core-book3s.c | 2 --
1 file changed, 2 d
Incase of random sampling, there can be scenarios where
Sample Instruction Address Register(SIAR) may not latch
to the sampled instruction and could result in
the value of 0. In these scenarios it is preferred to
return regs->nip. These corner cases are seen in the
previous generation (p9) also.
Le 18/08/2021 à 15:19, Kajol Jain a écrit :
Incase of random sampling, there can be scenarios where
Sample Instruction Address Register(SIAR) may not latch
to the sampled instruction and could result in
the value of 0. In these scenarios it is preferred to
return regs->nip. These corner cases
On Thu, 12 Aug 2021 18:58:30 +0530, Aneesh Kumar K.V wrote:
> Similar to x86/s390 add a debugfs file to tune tlb_single_page_flush_ceiling.
> Also add a debugfs entry for tlb_local_single_page_flush_ceiling.
Applied to powerpc/next.
[1/2] powerpc/book3s64/radix: make tlb_single_page_flush_ceiling
On Tue, 3 Aug 2021 16:15:43 +0200, Sebastian Andrzej Siewior wrote:
> This is a tree wide replacement of the deprecated CPU hotplug functions
> which are only wrappers around the actual functions.
>
> Each patch is independent and can be picked up by the relevant maintainer.
>
> [...]
Applied to
On Tue, 13 Apr 2021 16:38:09 + (UTC), Christophe Leroy wrote:
> powerpc BUG_ON() and WARN_ON() are based on using twnei instruction.
>
> For catching simple conditions like a variable having value 0, this
> is efficient because it does the test and the trap at the same time.
> But most conditi
On Tue, 20 Jul 2021 15:42:07 +0200, Cédric Le Goater wrote:
> The XIVE interrupt controller on P10 can automatically save and
> restore the state of the interrupt registers under the internal NVP
> structure representing the VCPU. This saves a costly store/load in
> guest entries and exits.
>
> Th
On Mon, 19 Jul 2021 15:06:14 +0200, Cédric Le Goater wrote:
> There is no need to use the lockup detector ("noirqdebug") for IPIs.
> The ipistorm benchmark measures a ~10% improvement on high systems
> when this flag is set.
Applied to powerpc/next.
[1/1] powerpc: use IRQF_NO_DEBUG for IPIs
On Sun, 27 Jun 2021 17:09:18 + (UTC), Christophe Leroy wrote:
> Last user of in_kernel_text() stopped using in with
> commit 549e8152de80 ("powerpc: Make the 64-bit kernel as a
> position-independent executable").
>
> Generic function is_kernel_text() does the same.
>
> So remote it.
Applied
On Thu, 5 Aug 2021 11:20:05 +1000, Anton Blanchard wrote:
> We shouldn't need legacy ptys, and disabling the option improves boot
> time by about 0.5 seconds.
Applied to powerpc/next.
[1/1] powerpc/configs: Disable legacy ptys on microwatt defconfig
https://git.kernel.org/powerpc/c/9b49f979
On Thu, 12 Aug 2021 18:52:18 +0530, Aneesh Kumar K.V wrote:
> Form2 associativity adds a much more flexible NUMA topology layout
> than what is provided by Form1. More details can be found in patch 7.
>
> $ numactl -H
> ...
> node distances:
> node 0 1 2 3
> 0: 10 11 222 33
> 1: 4
On Thu, 5 Aug 2021 17:56:49 +1000, Alexey Kardashevskiy wrote:
> The powernv_get_random_long() does not work in nested KVM (which is
> pseries) and produces a crash when accessing in_be64(rng->regs) in
> powernv_get_random_long().
>
> This replaces powernv_get_random_long with the ppc_md machine h
On Mon, 5 Jul 2021 12:00:50 + (UTC), Christophe Leroy wrote:
> Commit 3ccfebedd8cf ("powerpc, membarrier: Skip memory barrier in
> switch_mm()") added some logic to skip the smp_mb() in
> switch_mm_irqs_off() before the call to switch_mmu_context().
>
> However, on non SMP smp_mb() is just a c
On Wed, 4 Aug 2021 11:37:24 +1000, Jordan Niethe wrote:
> This is the same as commit acdad8fb4a15 ("powerpc: Force inlining of
> mmu_has_feature to fix build failure") but for radix_enabled(). The
> config in the linked bugzilla causes the following build failure:
>
> LD .tmp_vmlinux.kallsym
On Thu, 1 Jul 2021 15:27:18 +0200, Cédric Le Goater wrote:
> This series adds support for MSI IRQ domains on top of the XICS (P8)
> and XIVE (P9/P10) IRQ domains for the PowerNV (baremetal) and pSeries
> (VM) platforms. It should simplify and improve IRQ affinity of PCI
> MSIs under these PowerPC p
On Tue, 3 Aug 2021 16:59:55 +0200 (CEST), Julia Lawall wrote:
> for_each_node_by_type should have of_node_put() before return.
>
> Generated by: scripts/coccinelle/iterators/for_each_child.cocci
Applied to powerpc/next.
[1/1] powerpc/kexec: fix for_each_child.cocci warning
https://git.kern
On Tue, 11 May 2021 09:31:36 +0200, Laurent Dufour wrote:
> When a LPAR is migratable, we should consider the maximum possible NUMA
> node instead the number of NUMA node from the actual system.
>
> The DT property 'ibm,current-associativity-domains' is defining the maximum
> number of nodes the L
On Mon, 17 May 2021 11:06:06 +0200, Laurent Dufour wrote:
> After a LPM, the device tree node ibm,dynamic-reconfiguration-memory may be
> updated by the hypervisor in the case the NUMA topology of the LPAR's
> memory is updated.
>
> This is handled by the kernel, but the memory's node is not updat
On Thu, 29 Apr 2021 19:49:08 +0200, Laurent Dufour wrote:
> When a CPU is hot added, the CPU ids are taken from the available mask from
> the lower possible set. If that set of values was previously used for CPU
> attached to a different node, this seems to application like if these CPUs
> have mig
On Sun, 1 Aug 2021 09:38:17 +0200, Emmanuel Gil Peyrot wrote:
> The OTP is a read-only memory area which contains various keys and
> signatures used to decrypt, encrypt or verify various pieces of storage.
>
> Its size depends on the console, it is 128 bytes on the Wii and
> 1024 bytes on the Wii
On Thu, 29 Jul 2021 23:19:35 +0900, Masahiro Yamada wrote:
> Commit c913e5f95e54 ("powerpc/boot: Don't install zImage.* from make
> install") added the zInstall target to arch/powerpc/boot/Makefile,
> but you cannot use it since the corresponding hook is missing in
> arch/powerpc/Makefile.
>
> It
On Wed, 28 Jul 2021 23:26:04 +0530, Parth Shah wrote:
> Changes from v1 -> v2:
> - Based on Gautham's comments, use a separate thread_group_l3_cache_map
> and modify parsing code to build cache_map for L3. This makes the
> cache_map building code isolated from the parsing code.
> v1 can be foun
On Tue, 3 Aug 2021 14:15:47 -0700, Nathan Chancellor wrote:
> After commit 7cbd631d4dec ("cpuidle: pseries: Fixup CEDE0 latency only
> for POWER10 onwards"), pseries_idle_probe() is no longer inlined when
> compiling with clang, which causes a modpost warning:
>
> WARNING: modpost: vmlinux.o(.text
On Wed, 21 Jul 2021 00:15:04 +1000, Nicholas Piggin wrote:
> If an interrupt is taken in kernel mode, always use SIAR for it rather than
> looking at regs_sipr. This prevents samples piling up around interrupt
> enable (hard enable or interrupt replay via soft enable) in PMUs / modes
> where the PR
On Wed, 28 Jul 2021 17:34:59 +0530, Pratik R. Sampat wrote:
> v1: https://lkml.org/lkml/2021/7/26/1509
> Changelog v1-->v2:
> Based on comments from Gautham,
> 1. Included a #define for MAX_NR_CHIPS instead of hardcoding the
> allocation.
>
> Pratik R. Sampat (1):
> cpufreq:powernv: Fix init_chi
On Sat, Jul 31, 2021 at 5:30 AM Nick Desaulniers
wrote:
>
> On Thu, Jul 29, 2021 at 7:22 AM Masahiro Yamada wrote:
> >
> > Currently, the install target in arch/powerpc/Makefile descends into
> > arch/powerpc/boot/Makefile to invoke the shell script, but there is no
> > good reason to do so.
>
>
On 8/18/21 9:05 AM, Michael Ellerman wrote:
Laurent reported that STRICT_MODULE_RWX was causing intermittent crashes
on one of his systems:
kernel tried to execute exec-protected page (c00804073278) - exploit
attempt? (uid: 0)
BUG: Unable to handle kernel instruction fetch
Faulting
On Fri, Aug 13, 2021 at 04:08:13PM +1000, Nicholas Piggin wrote:
> This one possibly the branches end up in predictors, whereas conditional
> trap is always just speculated not to hit. Branches may also have a
> throughput limit on execution whereas trap could be more (1 per cycle
> vs 4 per cycle
While debugging an issue, we wanted to check whether the arch specific
kernel memmove implementation is correct. This selftest could help test that.
Suggested-by: Aneesh Kumar K.V
Suggested-by: Vaibhav Jain
Signed-off-by: Ritesh Harjani
---
tools/testing/selftests/powerpc/Makefile | 1 +
On 18/08/2021 14:05, Michael Ellerman wrote:
> Laurent reported that STRICT_MODULE_RWX was causing intermittent crashes
> on one of his systems:
>
> kernel tried to execute exec-protected page (c00804073278) - exploit
> attempt? (uid: 0)
> BUG: Unable to handle kernel instruction fetch
>
On 8/18/21 6:58 PM, Christophe Leroy wrote:
>
>
> Le 18/08/2021 à 15:19, Kajol Jain a écrit :
>> Incase of random sampling, there can be scenarios where
>> Sample Instruction Address Register(SIAR) may not latch
>> to the sampled instruction and could result in
>> the value of 0. In these scen
Minor optimization in the 'perf_instruction_pointer' function code by
making use of stack siar instead of mfspr.
Fixes: 75382aa72f06 ("powerpc/perf: Move code to select SIAR or pt_regs
into perf_read_regs")
Signed-off-by: Kajol Jain
---
arch/powerpc/perf/core-book3s.c | 2 +-
1 file changed, 1 i
Drop the case of returning 0 as instruction pointer since kernel
never executes at 0 and userspace almost never does either.
Fixes: e6878835ac47 ("powerpc/perf: Sample only if SIAR-Valid
bit is set in P7+")
Signed-off-by: Kajol Jain
---
arch/powerpc/perf/core-book3s.c | 2 --
1 file changed, 2 d
Incase of random sampling, there can be scenarios where
Sample Instruction Address Register(SIAR) may not latch
to the sampled instruction and could result in
the value of 0. In these scenarios it is preferred to
return regs->nip. These corner cases are seen in the
previous generation (p9) also.
P
Hi Xianting,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on char-misc/char-misc-testing soc/for-next v5.14-rc6
next-20210818]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
If an error occurs after 'of_find_node_by_path()', the reference taken for
'root' will never be released and some memory will leak.
Instead of adding an error handling path and modifying all the
'return -SOMETHING' into 'goto errorpath', use 'devm_add_action_or_reset()'
to release the reference wh
On Wed, Aug 18, 2021 at 08:42:18AM +0200, Christophe Leroy wrote:
>
>
> Le 18/08/2021 à 08:05, Kees Cook a écrit :
> > In preparation for FORTIFY_SOURCE performing compile-time and run-time
> > field bounds checking for memset(), avoid intentionally writing across
> > neighboring fields.
> >
> >
This patch prevents the following sparse warning.
arch/powerpc/kernel/tau_6xx.c:199:1: sparse: sparse: symbol 'tau_work'
was not declared. Should it be static?
Reported-by: kernel test robot
Signed-off-by: Finn Thain
---
arch/powerpc/kernel/tau_6xx.c | 2 +-
1 file changed, 1 insertion(+), 1 d
在 2021/8/18 上午11:17, Jiri Slaby 写道:
Hi,
On 17. 08. 21, 15:22, Xianting Tian wrote:
As well known, hvc backend can register its opertions to hvc backend.
the opertions contain put_chars(), get_chars() and so on.
"operations". And there too:
Some hvc backend may do dma in its opertions. eg,
On 18/08/21 10:45 pm, Kajol Jain wrote:
Minor optimization in the 'perf_instruction_pointer' function code by
making use of stack siar instead of mfspr.
Fixes: 75382aa72f06 ("powerpc/perf: Move code to select SIAR or pt_regs
into perf_read_regs")
Signed-off-by: Kajol Jain
Tested this patc
On 13/08/21 1:51 pm, Kajol Jain wrote:
H_GetPerformanceCounterInfo (0xF080) hcall returns the counter data in the
result buffer. Result buffer has specific format defined in the PAPR
specification. One of the field is counter offset and width of the counter
data returned.
Counter data are ret
In those hot functions that are called at every interrupt, any saved
cycle is worth it.
interrupt_exit_user_prepare() and interrupt_exit_kernel_prepare() are
called from three places:
- From entry_32.S
- From interrupt_64.S
- From interrupt_exit_user_restart() and interrupt_exit_kernel_restart()
40x and BOOKE don't have MSR_RI therefore all tests involving
MSR_RI may be problematic on those plateforms.
Create helpers to check or set MSR_RI in regs, and use them
in common code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/ptrace.h | 23 +++
ar
40x and BOOKE don't have MSR_RI.
Define MSR_RI only for platforms where it exists. For the other ones,
defines it as BUILD_BUG for C and do not define it for ASM.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 4
arch/powerpc/include/asm/reg_booke.h | 6 +++---
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