Re: [PATCH 1/2] mm/mprotect: Call arch_validate_prot under mmap_lock and with length

Hi Khalid, On Wed, Oct 07, 2020 at 02:14:09PM -0600, Khalid Aziz wrote: > On 10/7/20 1:39 AM, Jann Horn wrote: > > arch_validate_prot() is a hook that can validate whether a given set of > > protection flags is valid in an mprotect() operation. It is given the set > > of protection flags and the a

[PATCH] powerpc/603: Always fault when _PAGE_ACCESSED is not set

The kernel expects pte_young() to work regardless of CONFIG_SWAP. Make sure a minor fault is taken to set _PAGE_ACCESSED when it is not already set, regardless of the selection of CONFIG_SWAP. Fixes: 84de6ab0e904 ("powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers.") Cc: sta...@vger.k

[PATCH 1/4] powerpc/8xx: Fix instruction TLB miss exception with perf enabled

When perf is enabled, r11 must also be restored when CONFIG_HUGETLBFS is selected. Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.") Cc: sta...@vger.kernel.org Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 2 +- 1 file changed, 1 inserti

[PATCH 2/4] powerpc/8xx: Fix TLB Miss exceptions with CONFIG_SWAP

When CONFIG_SWAP is set, _PAGE_ACCESSED gets ANDed with _PAGE_PRESENT. But during several changes of _PAGE_ACCESSED value, this operation which is based on bit rotation has been forgotten. As of today it doesn't work. Update to the rotation to the correct number of bits. Fixes: 5f356497c384 ("po

[PATCH 3/4] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set

The kernel expects pte_young() to work regardless of CONFIG_SWAP. Make sure a minor fault is taken to set _PAGE_ACCESSED when it is not already set, regardless of the selection of CONFIG_SWAP. This adds at least 3 instructions to the TLB miss exception handlers fast path. Following patch will red

[PATCH] powerpc/40x: Always fault when _PAGE_ACCESSED is not set

The kernel expects pte_young() to work regardless of CONFIG_SWAP. Make sure a minor fault is taken to set _PAGE_ACCESSED when it is not already set, regardless of the selection of CONFIG_SWAP. Fixes: 2c74e2586bb9 ("powerpc/40x: Rework 40x PTE access and TLB miss") Cc: sta...@vger.kernel.org Signe

[PATCH 4/4] powerpc/8xx: Manage _PAGE_ACCESSED through APG bits in L1 entry

When _PAGE_ACCESSED is not set, a minor fault is expected. To do this, TLB miss exception ANDs _PAGE_PRESENT and _PAGE_ACCESSED into the L2 entry valid bit. To simplify the processing and reduce the number of instructions in TLB miss exceptions, manage it as an APG bit and get it next to _PAGE_GUA

[PATCH] powerpc/mm: Fix verification of MMU_FTR_TYPE_44x

MMU_FTR_TYPE_44x cannot be checked by cpu_has_feature() Use mmu_has_feature() instead Fixes: 23eb7f560a2a ("powerpc: Convert flush_icache_range & friends to C") Cc: sta...@vger.kernel.org Signed-off-by: Christophe Leroy --- arch/powerpc/mm/mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletio

Re: [PATCH RFC PKS/PMEM 10/58] drivers/rdma: Utilize new kmap_thread()

-ira.we...@intel.com wrote: - >To: "Andrew Morton" , "Thomas Gleixner" >, "Ingo Molnar" , "Borislav >Petkov" , "Andy Lutomirski" , "Peter >Zijlstra" >From: ira.we...@intel.com >Date: 10/09/2020 09:52PM >Cc: "Ira Weiny" , "Mike Marciniszyn" >, "Dennis Dalessandro" >, "Doug Ledford" , >"Jas

Re: [PATCH RFC PKS/PMEM 09/58] drivers/gpu: Utilize new kmap_thread()

On Sat, Oct 10, 2020 at 12:03:49AM +0200, Daniel Vetter wrote: > On Fri, Oct 09, 2020 at 12:49:44PM -0700, ira.we...@intel.com wrote: > > From: Ira Weiny > > > > These kmap() calls in the gpu stack are localized to a single thread. > > To avoid the over head of global PKRS updates use the new kma

[PATCH v5 0/5] powerpc/sstep: VSX 32-byte vector paired load/store instructions

VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxv

[PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

From: Balamuruhan S Unconditional emulation of prefixed instructions will allow emulation of them on Power10 predecessors which might cause issues. Restrict that. Fixes: 3920742b92f5 ("powerpc sstep: Add support for prefixed fixed-point arithmetic") Fixes: 50b80a12e4cc ("powerpc sstep: Add supp

[PATCH v5 2/5] powerpc/sstep: Cover new VSX instructions under CONFIG_VSX

Recently added Power10 prefixed VSX instruction are included unconditionally in the kernel. If they are executed on a machine without VSX support, it might create issues. Fix that. Also fix one mnemonics spelling mistake in comment. Fixes: 50b80a12e4cc ("powerpc sstep: Add support for prefixed loa

[PATCH v5 3/5] powerpc/sstep: Support VSX vector paired storage access instructions

From: Balamuruhan S VSX Vector Paired instructions loads/stores an octword (32 bytes) from/to storage into two sequential VSRs. Add emulation support for these new instructions: * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Prefixed Load VSX Vector Paired (plxvp

[PATCH v5 4/5] powerpc/ppc-opcode: Add encoding macros for VSX vector paired instructions

From: Balamuruhan S Add instruction encodings, DQ, D0, D1 immediate, XTP, XSP operands as macros for new VSX vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Prefixed Load VSX Vector Paired (plxvp) * Store VSX Vector Paired (stxvp) *

[PATCH v5 5/5] powerpc/sstep: Add testcases for VSX vector paired load/store instructions

From: Balamuruhan S Add testcases for VSX vector paired load/store instructions. Sample o/p: emulate_step_test: lxvp : PASS emulate_step_test: stxvp : PASS emulate_step_test: lxvpx : PASS emulate_step_test: stxvpx : PASS emulate_step_test: plxvp