On 7/8/20 7:42 AM, Michael Ellerman wrote:
"Aneesh Kumar K.V" writes:
From: Bharata B Rao
remove_pagetable() isn't freeing PUD table. This causes memory
leak during memory unplug. Fix this.
Fixes: 4b5d62ca17a1 ("powerpc/mm: add radix__remove_section_mapping()")
Fixes: ??
cheers
Sign
On 7/7/20 1:57 AM, Nicholas Piggin wrote:
Yes, powerpc could certainly get more performance out of the slow
paths, and then there are a few parameters to tune.
We don't have a good alternate patching for function calls yet, but
that would be something to do for native vs pv.
And then there seem
https://bugzilla.kernel.org/show_bug.cgi?id=208197
--- Comment #7 from Michael Ellerman (mich...@ellerman.id.au) ---
I couldn't really make sense of your bisect log, it doesn't have any good/bad
commits in it.
And I don't see how reverting a merge of v5.7-rc7 can be helping, because you
said v5.7
Hi Palmer,
Le 6/7/20 à 3:59 AM, Alexandre Ghiti a écrit :
This patchset originally implemented relocatable kernel support but now
also moves the kernel mapping into the vmalloc zone.
The first patch explains why w
On Fri, Jun 26, 2020 at 02:22:11PM -0700, Brendan Higgins wrote:
> On Fri, Jun 26, 2020 at 2:20 PM Kees Cook wrote:
> >
> > On Fri, Jun 26, 2020 at 02:09:06PM -0700, Brendan Higgins wrote:
> > > Add a linker section where KUnit can put references to its test suites.
> > > This patch is the first s
On Fri, Jun 26, 2020 at 02:09:13PM -0700, Brendan Higgins wrote:
> Remove KUnit from init calls entirely, instead call directly from
> kernel_init().
The commit log does not explain *why*.
> Co-developed-by: Alan Maguire
> Signed-off-by: Alan Maguire
> Signed-off-by: Brendan Higgins
> Reviewed
"Aneesh Kumar K.V" writes:
> To enable memory unplug without splitting kernel page table
> mapping, we force the max mapping size to the LMB size. LMB
> size is the unit in which hypervisor will do memory add/remove
> operation.
>
> This implies on pseries system, we now end up mapping
Please exp
Le 07/07/2020 à 21:02, Christophe Leroy a écrit :
Le 07/07/2020 à 14:44, Christophe Leroy a écrit :
Le 30/06/2020 à 03:19, Michael Ellerman a écrit :
Michael Ellerman writes:
Christophe Leroy writes:
Hi Michael,
I see this patch is marked as "defered" in patchwork, but I can't see
a
Last series[1] was to add basic infrastructure support for more than
one watchpoint on Book3S powerpc. This series actually enables the 2nd
DAWR for baremetal and powervm. Kvm guest is still not supported.
v2:
https://lore.kernel.org/linuxppc-dev/20200604033443.70591-1-ravi.bango...@linux.ibm.co
Milton Miller reported that we are aligning start and end address to
wrong size SZ_512M. It should be SZ_512. Fix that.
While doing this change I also found a case where ALIGN() comparison
fails. Within a given aligned range, ALIGN() of two addresses does not
match when start address is pointing t
Pedro Miraglia Franco de Carvalho noticed that on p8, DAR value is
inconsistent with different type of load/store. Like for byte,word
etc. load/stores, DAR is set to the address of the first byte of
overlap between watch range and real access. But for quadword load/
store it's set to the address of
CPU_FTR_DAWR is by default enabled for host via CPU_FTRS_DT_CPU_BASE
(controlled by CONFIG_PPC_DT_CPU_FTRS). But cpu-features device-tree
node is not PAPR compatible and thus not yet used by kvm or pHyp
guests. Enable watchpoint functionality on power10 guest (both kvm
and powervm) by adding CPU_FT
Add new device-tree feature for 2nd DAWR. If this feature is present,
2nd DAWR is supported, otherwise not.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/cputable.h | 7 +--
arch/powerpc/kernel/dt_cpu_ftrs.c | 7 +++
2 files changed, 12 insertions(+), 2 deletions(-)
diff -
As per the PAPR, bit 0 of byte 64 in pa-features property indicates
availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Host generally uses "cpu-features",
which masks "pa-features". But "cpu-features" are still not used for
guests and thus this change i
Current H_SET_MODE hcall macro name for setting/resetting DAWR0 is
H_SET_MODE_RESOURCE_SET_DAWR. Add suffix 0 to macro name as well.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hvcall.h | 2 +-
arch/powerpc/include/asm/plpar_wrappers.h | 2 +-
arch/powerpc/kvm/book3s_hv.c
2nd DAWR can be set/unset using H_SET_MODE hcall with resource value 5.
Enable powervm guest support with that. This has no effect on kvm guest
because kvm will return error if guest does hcall with resource value 5.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hvcall.h | 1
So far Book3S Powerpc supported only one watchpoint. Power10 is
introducing 2nd DAWR. Enable 2nd DAWR support for Power10.
Availability of 2nd DAWR will depend on CPU_FTR_DAWR1.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/cputable.h | 4 +++-
arch/powerpc/include/asm/hw_breakp
Power10 has removed 512 bytes boundary from match criteria. i.e. The watch
range can cross 512 bytes boundary.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/hw_breakpoint.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/hw_breakpoint.c
b/arch
Excerpts from Waiman Long's message of July 8, 2020 1:33 pm:
> On 7/7/20 1:57 AM, Nicholas Piggin wrote:
>> Yes, powerpc could certainly get more performance out of the slow
>> paths, and then there are a few parameters to tune.
>>
>> We don't have a good alternate patching for function calls yet,
Excerpts from Paul Menzel's message of July 8, 2020 3:42 am:
> Dear Nicholas,
>
>
> Am 07.07.20 um 09:03 schrieb Nicholas Piggin:
>> Excerpts from Paul Menzel's message of July 6, 2020 3:20 pm:
>
>>> Am 06.07.20 um 02:41 schrieb Nicholas Piggin:
Excerpts from Paul Menzel's message of July 5
Excerpts from Mathieu Desnoyers's message of July 7, 2020 9:25 pm:
> - On Jul 7, 2020, at 1:50 AM, Nicholas Piggin npig...@gmail.com wrote:
>
>> Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm:
>>>
>>>
>>> Le 06/07/2020 à 04:18, Nicholas Piggin a écrit :
diff --git a/ar
Hi Randy
On Tue, Jul 07, 2020 at 11:04:00AM -0700, Randy Dunlap wrote:
> Drop the doubled word "and".
>
> Signed-off-by: Randy Dunlap
> Cc: Jonathan Corbet
> Cc: linux-...@vger.kernel.org
> Cc: James (Qian) Wang
> Cc: Liviu Dudau
> Cc: Mihail Atanassov
> Cc: Mali DP Maintainers
> ---
> Doc
> From: Christian Zigotzky
> Sent: Tuesday, July 7, 2020 9:26 PM
> To: Madalin Bucur (OSS)
> Cc: mad skateman ; Camelia Alexandra Groza
> ;
> linuxppc-...@ozlabs.org; net...@vger.kernel.org; R.T.Dickinson
> ;
> Darren Stevens
> Subject: Re: FSL P5020/P5040: DPAA Ethernet issue with the latest
On Tue, 7 Jul 2020 11:03:54 -0700, Randy Dunlap wrote:
> Drop doubled words in various parts of Documentation/.
>
> [...]
Applied to 5.9/scsi-queue, thanks!
[17/20] scsi: advansys: docs: Eliminate duplicated word
https://git.kernel.org/mkp/scsi/c/3010dfb0b77c
--
Martin K. Petersen
On 08 July 2020 at 08:03 am, Madalin Bucur (OSS) wrote:
From: Christian Zigotzky
Sent: Tuesday, July 7, 2020 9:26 PM
To: Madalin Bucur (OSS)
Cc: mad skateman ; Camelia Alexandra Groza
;
linuxppc-...@ozlabs.org; net...@vger.kernel.org; R.T.Dickinson
;
Darren Stevens
Subject: Re: FSL P5020/P50
On 7/8/20 10:14 AM, Michael Ellerman wrote:
"Aneesh Kumar K.V" writes:
To enable memory unplug without splitting kernel page table
mapping, we force the max mapping size to the LMB size. LMB
size is the unit in which hypervisor will do memory add/remove
operation.
This implies on pseries syste
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