Sebastian Andrzej Siewior writes:
> On 2020-03-19 03:04:59 [-0700], Christoph Hellwig wrote:
>> But I wonder how alive the whole PS3 support is to start with..
>
> OtherOS can only be used on "old" PS3 which do not have have their
> firmware upgraded past version 3.21, released April 1, 2010 [0].
Michael Ellerman's on March 19, 2020 2:15 pm:
> Nicholas Piggin writes:
>> This allows the 64s hash MMU code to be compiled out if radix is
>> selected. This saves about 128kB kernel image size (90kB text) on
>> powernv_defconfig minus KVM, 40kB on a tiny config.
>
> TBH my feelings are:
> - the
Christophe Leroy writes:
> Move ADV_DEBUG_REGS functions out of ptrace.c, into
> ptrace-adv.c and ptrace-noadv.c
>
> Signed-off-by: Christophe Leroy
> ---
> v4: Leave hw_breakpoint.h for ptrace.c
> ---
> arch/powerpc/kernel/ptrace/Makefile | 4 +
> arch/powerpc/kernel/ptrace/ptrace-adv.c
Ganesh's on March 18, 2020 12:35 am:
>
>
> On 3/17/20 3:31 PM, Nicholas Piggin wrote:
>> Ganesh's on March 16, 2020 9:47 pm:
>>>
>>> On 3/14/20 9:18 AM, Nicholas Piggin wrote:
Ganesh Goudar's on March 14, 2020 12:04 am:
> MCE handling on pSeries platform fails as recent rework to use com
Hi Jason,
I tried to compile this series and got the following error:
/home/dja/dev/linux/linux/arch/powerpc/mm/nohash/kaslr_booke.c: In function
‘kaslr_early_init’:
/home/dja/dev/linux/linux/arch/powerpc/mm/nohash/kaslr_booke.c:357:33: error:
‘linear_sz’ may be used uninitialized in this funct
The previous commit reduced the amount of code that is run before we
setup a paca. However there are still a few remaining functions that
run with no paca, or worse, with an arbitrary value in r13 that will
be used as a paca pointer.
In particular the stack protector canary is stored in the paca,
From: Daniel Axtens
Currently we set up the paca after parsing the device tree for CPU
features. Prior to that, r13 contains random data, which means there
is random data in r13 while we're running the generic dt parsing code.
This random data varies depending on whether we boot through a vmlinu
Christophe Leroy's on March 19, 2020 7:18 pm:
>
>
> Le 25/02/2020 à 18:35, Nicholas Piggin a écrit :
>> System call entry and particularly exit code is beyond the limit of what
>> is reasonable to implement in asm.
>>
>> This conversion moves all conditional branches out of the asm code,
>> exce
On Thu, Mar 19, 2020 at 02:47:58PM +0100, Vlastimil Babka wrote:
> diff --git a/mm/slub.c b/mm/slub.c
> index 17dc00e33115..7113b1f9cd77 100644
> --- a/mm/slub.c
> +++ b/mm/slub.c
> @@ -1973,8 +1973,6 @@ static void *get_partial(struct kmem_cache *s, gfp_t
> flags, int node,
>
> if (node =
This series renames pmd_mknotpresent() as pmd_mknotvalid(). Before that it
drops an existing pmd_mknotpresent() definition from powerpc platform which
was never required as it defines it's pmdp_invalidate() through subscribing
__HAVE_ARCH_PMDP_INVALIDATE. This does not create any functional change.
Platform needs to define pmd_mknotpresent() for generic pmdp_invalidate()
only when __HAVE_ARCH_PMDP_INVALIDATE is not subscribed. Otherwise platform
specific pmd_mknotpresent() is not required. Hence just drop it.
Cc: Benjamin Herrenschmidt
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: linuxppc-
On Fri, 2020-03-06 at 14:40 +0800, Jason Yan wrote:
> @@ -38,5 +41,29 @@ bit of the entropy to decide the index of the 64M zone.
> Then we chose a
>
>kernstart_virt_addr
>
> +
> +KASLR for Freescale BookE64
> +---
> +
> +The implementation
A future revision of the ISA will introduce prefixed instructions. A
prefixed instruction is composed of a 4-byte prefix followed by a
4-byte suffix.
All prefixes have the major opcode 1. A prefix will never be a valid
word instruction. A suffix may be an existing word instruction or a
new instruc
For modifying instructions in xmon, patch_instruction() can serve the
same role that store_inst() is performing with the advantage of not
being specific to xmon. In some places patch_instruction() is already
being using followed by store_inst(). In these cases just remove the
store_inst(). Otherwis
To execute an instruction out of line after a breakpoint, the NIP is set
to the address of struct bpt::instr. Here a copy of the instruction that
was replaced with a breakpoint is kept, along with a trap so normal flow
can be resumed after XOLing. The struct bpt's are located within the
data sectio
Currently unsigned ints are used to represent instructions on powerpc.
This has worked well as instructions have always been 4 byte words.
However, a future ISA version will introduce some changes to
instructions that mean this scheme will no longer work as well. This
change is Prefixed Instruction
In preparation for instructions having a more complex data type start
using a macro, PPC_INST(), for making an instruction out of a u32.
Currently this does nothing, but it will allow for creating a data type
that can represent prefixed instructions.
Signed-off-by: Jordan Niethe
---
v4: New to se
In preparation for using an instruction data type that can not be used
directly with the '&' operator, use a function to mask instructions.
Signed-off-by: Jordan Niethe
---
v4: New to series
---
arch/powerpc/include/asm/sstep.h | 6 +++---
arch/powerpc/kernel/align.c| 2 +-
arch/powe
In preparation for using a data type for instructions that can not be
directly used with the '>>' operator use a function for getting the op
code of an instruction.
Signed-off-by: Jordan Niethe
---
v4: New to series
---
arch/powerpc/kernel/align.c | 4 ++--
arch/powerpc/lib/code-patching.c
In preparation for an instruction data type that can not be directly
used with the '==' operator use functions for checking equality and
nullity.
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/optprobes.c | 2 +-
arch/powerpc/kernel/trace/ftrace.c | 33 +++-
In preparation for prefixed instructions where all instructions are no
longer words, use an accessor for getting a word instruction as a u32
from the instruction data type.
Signed-off-by: Jordan Niethe
---
v4: New to series
---
arch/powerpc/kernel/align.c | 2 +-
arch/powerpc/kernel/k
Prefixed instructions will mean there are instructions of different
length. As a result dereferencing a pointer to an instruction will not
necessarily give the desired result. Introduce a function for reading
instructions from memory into the instruction data type.
Signed-off-by: Jordan Niethe
--
test_translate_branch() uses two pointers to instructions within a
buffer, p and q, to test patch_branch(). The pointer arithmetic done on
them assumes a size of 4. This will not work if the instruction length
changes. Instead do the arithmetic relative to the void * to the buffer.
Signed-off-by:
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a faci
Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
exception is a prefixed instruction that crosses a 64-byte boundary.
Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
instructions.
Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
Alignment interrupts can be caused by prefixed instructions accessing
memory. Prefixed instructions are not permitted to cross 64-byte
boundaries. If they do the alignment interrupt is invoked with SRR1
BOUNDARY bit set. If this occurs send a SIGBUS to the offending process
if in user mode. If in
For powerpc64, redefine the ppc_inst type so both word and prefixed
instructions can be represented. On powerpc32 the type will remain the
same. Update places which had assumed instructions to be 4 bytes long.
Signed-off-by: Jordan Niethe
---
v4: New to series
---
arch/powerpc/include/asm/code-
This adds emulation support for the following prefixed integer
load/stores:
* Prefixed Load Byte and Zero (plbz)
* Prefixed Load Halfword and Zero (plhz)
* Prefixed Load Halfword Algebraic (plha)
* Prefixed Load Word and Zero (plwz)
* Prefixed Load Word Algebraic (plwa)
* Prefixed Load
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
v3: Since we moved the prefixed loads/stores into the load/store switch
statement it no longer makes sense to have paddi in there, so mov
On 2020-03-13 19:36:12 Fri, Ganesh Goudar wrote:
> If we hit UE at an instruction with a fixup entry, flag to
> ignore the event and set nip to continue execution at the
> fixup entry.
> For powernv this changes are already made by commit
> 895e3dceeb97 ("powerpc/mce: Handle UE event for memcpy_mcs
On Wed, 18 Mar 2020, Thomas Gleixner wrote:
--- a/include/linux/rcuwait.h
+++ b/include/linux/rcuwait.h
@@ -3,6 +3,7 @@
#define _LINUX_RCUWAIT_H_
#include
+#include
So this is causing build to fail for me:
CC arch/x86/boot/compressed/cmdline.o
arch/x86/boot/compressed/cmdline.c:5:20:
在 2020/3/20 11:19, Daniel Axtens 写道:
Hi Jason,
I tried to compile this series and got the following error:
/home/dja/dev/linux/linux/arch/powerpc/mm/nohash/kaslr_booke.c: In function
‘kaslr_early_init’:
/home/dja/dev/linux/linux/arch/powerpc/mm/nohash/kaslr_booke.c:357:33: error:
‘linear_s
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