V2 -> V3:
in [2/2], EXPORT_SYMBOL(new_property) and EXPORT_SYMBOL_GPL(of_add_property)
To: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Hari Bathini
Cc: Aneesh Kumar K.V
Cc: Oliver O'Halloran
Cc: Dan Williams
Cc: Andrew Donnellan
C
Splitting out new_property() for coming reusing and moving it to
of_helpers.c.
Also do some coding style cleanup.
Signed-off-by: Pingfan Liu
To: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Hari Bathini
Cc: Aneesh Kumar K.V
Cc: Oliver
At present, plpar_hcall(H_SCM_BIND_MEM, ...) takes a very long time, so
if dumping to fsdax, it will take a very long time.
Take a closer look, during the papr_scm initialization, the only
configuration is through drc_pmem_bind()-> plpar_hcall(H_SCM_BIND_MEM,
...), which helps to set up the bound
On Tue, 3 Mar 2020 20:18:18 +0100
Cédric Le Goater wrote:
> >> BTW: I figured, I dont need this intermin patch to disable xive for
> >> secure VM. Just doing "svm=on xive=off" on the kernel command line is
> >> sufficient for now. *
> >>
> >
> > No it is not. If the hypervisor doesn't
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
The controller can report a number of statistics that are useful
in evaluating the performance and reliability of the card.
This patch exposes this information via an IOCTL.
Signed-off-by: Alastair D'Silva
---
arch
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
Some of the interrupts that the card generates are better handled
by the userspace daemon, in particular:
Controller Hardware/Firmware Fatal
Controller Dump Available
Error Log available
This patch allows a userspace a
There's two different paths through the sigreturn code, depending on
whether the VDSO is mapped or not. We recently discovered a bug in the
unmapped case, because it's not commonly used these days.
So add a test that sends itself a signal, then moves the VDSO, takes
another signal and finally unma
Le 28/02/2020 à 07:12, Andrew Donnellan a écrit :
On 21/2/20 2:27 pm, Alastair D'Silva wrote:
From: Alastair D'Silva
When health & performance data is requested from the controller,
it responds with an error log containing the requested information.
This patch allows the request to me issu
On Tue, 3 Mar 2020 10:56:45 -0800
Ram Pai wrote:
> On Tue, Mar 03, 2020 at 06:45:20PM +0100, Greg Kurz wrote:
> > On Tue, 3 Mar 2020 09:02:05 -0800
> > Ram Pai wrote:
> >
> > > On Tue, Mar 03, 2020 at 07:50:08AM +0100, Cédric Le Goater wrote:
> > > > On 3/3/20 12:32 AM, David Gibson wrote:
> >
> On Mar 4, 2020, at 1:49 AM, Christophe Leroy wrote:
>
> AFAIU, you are not taking an interrupt here. You are stuck in the
> pte_update(), most likely due to nested locks. Try with LOCKDEP ?
Not exactly sure what did you mean here, but the kernel has all lockdep enabled
and did not flag an
On Tue, 2020-03-03 at 23:43 -0800, James Bottomley wrote:
> On Tue, 2020-03-03 at 21:33 -0500, Nayna Jain wrote:
> > diff --git a/security/integrity/ima/Kconfig
> > b/security/integrity/ima/Kconfig
> > index 3f3ee4e2eb0d..d17972aa413a 100644
> > --- a/security/integrity/ima/Kconfig
> > +++ b/secur
On Tue, 2020-03-03 at 21:33 -0500, Nayna Jain wrote:
> Every time a new architecture defines the IMA architecture specific
> functions - arch_ima_get_secureboot() and arch_ima_get_policy(), the
> IMA
> include file needs to be updated. To avoid this "noise", this patch
> defines a new IMA Kconfig I
[Cc'ing Thomas Gleixner and x86 mailing list]
On Wed, 2020-03-04 at 08:14 +0100, Ard Biesheuvel wrote:
> On Wed, 4 Mar 2020 at 03:34, Nayna Jain wrote:
> >
> > Every time a new architecture defines the IMA architecture specific
> > functions - arch_ima_get_secureboot() and arch_ima_get_policy(),
On Wed, 04 Mar 2020 07:55:38 -0500
Mimi Zohar wrote:
> [Cc'ing Thomas Gleixner and x86 mailing list]
>
> On Wed, 2020-03-04 at 08:14 +0100, Ard Biesheuvel wrote:
> > On Wed, 4 Mar 2020 at 03:34, Nayna Jain wrote:
> > >
> > > Every time a new architecture defines the IMA architecture specific
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
The heartbeat admin command is a simple admin command that exercises
the communication mechanisms within the controller.
This patch issues a heartbeat command to the card during init to ensure
we can communicate with t
On Wed, Mar 04, 2020 at 11:59:48AM +0100, Greg Kurz wrote:
> On Tue, 3 Mar 2020 10:56:45 -0800
> Ram Pai wrote:
>
> > On Tue, Mar 03, 2020 at 06:45:20PM +0100, Greg Kurz wrote:
> > > On Tue, 3 Mar 2020 09:02:05 -0800
> > > Ram Pai wrote:
> > >
> > > > On Tue, Mar 03, 2020 at 07:50:08AM +0100, C
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
These IOCTLs provide low level access to the card to aid in debugging
controller/FPGA firmware.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/platforms/powernv/pmem/Kconfig | 6 +
arch/powerpc/platforms/powern
On Wed, 2020-03-04 at 07:35 -0500, Mimi Zohar wrote:
> On Tue, 2020-03-03 at 23:43 -0800, James Bottomley wrote:
> > On Tue, 2020-03-03 at 21:33 -0500, Nayna Jain wrote:
> > > diff --git a/security/integrity/ima/Kconfig
> > > b/security/integrity/ima/Kconfig
> > > index 3f3ee4e2eb0d..d17972aa413a 1
On Wed, Mar 04, 2020 at 11:59:48AM +0100, Greg Kurz wrote:
> On Tue, 3 Mar 2020 10:56:45 -0800
> Ram Pai wrote:
>
> > On Tue, Mar 03, 2020 at 06:45:20PM +0100, Greg Kurz wrote:
snip.
> > >
> > > This patch would allow at least to answer Cedric's question about
> > > kernel_irqchip=off, since
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
This patch retrieves proprietary formatted SMART data and makes it
available via ndctl. A later contribution will be made to ndctl to
parse this data.
Signed-off-by: Alastair D'Silva
---
Nothing new to add compared
[ ... ]
> (1) applied the patch which shares the EQ-page with the hypervisor.
> (2) set "kernel_irqchip=off"
> (3) set "ic-mode=xive"
you don't have to set the interrupt mode. xive should be negotiated
by default.
> (4) set "svm=on" on the kernel command line.
> (5) no changes to the hypervisor
A concept patch in Skiboot to illustrate the case wherein handling of
stop states for different DD versions of a CPU can be achieved by a
simple modification in the list of cpu_features.
As an example idle-stop1 is defined which uses P9_CPU_DD1 to define the
cpu feature.
Along with that, an implem
Design patch to introduce the idea of having a dependency structure for
idle-stop. The structure encapsulates the following:
1. Bitmask for version of idle-stop
2. Bitmask for propterties like ENABLE/DISABLE
3. Function pointer which helps handle how the stop must be invoked
The commit lays a foun
A design patch series illuminates the idea of handling different
versions of idle-stop, the properties they support and the
quirks that need to be handled before entering or after exiting stop.
It also adds a functionality to identify firmware-enabled-stop and set
the according bits to encapsulate
Concept patch demonstrating an idle-stop version discovery from the
device tree, along with population its support and versioning. It also
assigns the function pointer to handle any idle-stop specific quirks.
Signed-off-by: Pratik Rajesh Sampat
---
arch/powerpc/include/asm/processor.h | 1 +
a
Design patch that introduces the capability for firmware to handle the
stop states instead. A bit is set based on the discovery of the feature
and correspondingly also the responsibility to handle the stop states.
The commit does not contain calling into the firmware to utilize
firmware enabled st
Well, not quite removed yet... Mauro is looking at moving this to ReST,
but I think it would be better to trim or remove it.
boot-without-of.txt is an ancient document that first outlined
Flattened DeviceTree. The DT world has evolved a lot in the 15 years
since and boot-without-of.txt is pretty s
On power9, Virtual Accelerator Switchboard (VAS) allows user space or
kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE
instructions. NX provides various functionalities such as compression,
encryption and etc. But only compression (842 and GZIP formats) is
supported in L
This function allocates IRQ on a specific chip. VAS needs per chip
IRQ allocation and will have IRQ handler per VAS instance.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/xive.h | 9 -
arch/powerpc/sysdev/xive/native.c | 6 +++---
2 files changed, 11 insertions(+), 4 dele
pnv_ocxl_alloc_xive_irq() in ocxl.c allocates IRQ and gets trigger port
address. VAS also needs this function, but based on chip ID. So moved
this common function to xive/native.c.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/xive.h | 2 ++
arch/powerpc/platforms/powernv/ocx
Kernel sets fault address and status in CRB for NX page fault on user
space address after processing page fault. User space gets the signal
and handles the fault mentioned in CRB by bringing the page in to
memory and send NX request again.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren
Alloc IRQ and get trigger port address for each VAS instance. Kernel
register this IRQ per VAS instance and sets this port for each send
window. NX interrupts the kernel when it sees page fault.
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas.c | 34 +
Setup fault window for each VAS instance. When NX gets a fault on
request buffer, write fault CRBs in the corresponding fault FIFO and
then sends an interrupt to the OS.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/Makefile | 2 +-
arc
Setup thread IRQ handler per each VAS instance. When NX sees a fault
on CRB, kernel gets an interrupt and vas_fault_handler will be
executed to process fault CRBs. Read all valid CRBs from fault FIFO,
determine the corresponding send window from CRB and process fault
requests.
Signed-off-by: Suk
For each user space send window, register NX with fault window ID
and port value so that NX paste CRBs in this fault FIFO when it
sees fault on the request buffer.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-window.c | 15 +
Process close windows after its requests are completed. In multi-thread
applications, child can open a window but release FD will not be called
upon its exit. Parent thread will be closing it later upon its exit.
The parent can also send NX requests with this window and NX can
generate page faul
Dump FIFO entries if could not find send window and print CRB
for debugging.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-fault.c | 41 ++
1 file changed, 41 insertions(+)
diff --git a/arch/powerpc/platforms
System checkstops if RxFIFO overruns with more requests than the
maximum possible number of CRBs allowed in FIFO at any time. So
max credits value (rxattr.wcreds_max) is set and is passed to
vas_rx_win_open() by the the driver.
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas
For each fault CRB, update fault address in CRB (fault_storage_addr)
and translation error status in CSB so that user space can touch the
fault address and resend the request. If the user space passed invalid
CSB address send signal to process with SIGSEGV.
Signed-off-by: Sukadev Bhattiprolu
Si
NX expects OS to return credit for send window after processing each
fault. Also credit has to be returned even for fault window.
Signed-off-by: Sukadev Bhattiprolu
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-fault.c | 9 +
arch/powerpc/platforms/powernv/vas-w
Process can not close send window until all requests are processed.
Means wait until window state is not busy and send credits are
returned. Display debug messages in case taking longer to close the
window.
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-window.c | 28 ++
NX may be processing requests while trying to close window. Wait until
all credits are returned and then free send window from VAS instance.
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/powernv/vas-window.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/
On Wed, 2020-02-26 at 18:16 +1100, Daniel Axtens wrote:
> Hi Jason,
>
> > This is a try to implement KASLR for Freescale BookE64 which is based on
> > my earlier implementation for Freescale BookE32:
> > https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=131718
> >
> > The implementat
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
> The implementation for Freescale BookE64 is similar as BookE32. One
> difference is that Freescale BookE64 set up a TLB mapping of 1G during
> booting. Another difference is that ppc64 needs the kernel to be
> 64K-aligned. So we can randomize th
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
> The BSS section has already cleared out in the first pass. No need to
> clear it again. This can save some time when booting with KASLR
> enabled.
>
> Signed-off-by: Jason Yan
> Cc: Scott Wood
> Cc: Diana Craciun
> Cc: Michael Ellerman
> Cc
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
> The original kernel still exists in the memory, clear it now.
>
> Signed-off-by: Jason Yan
> Cc: Scott Wood
> Cc: Diana Craciun
> Cc: Michael Ellerman
> Cc: Christophe Leroy
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Cc: Nichola
On Wed, 2020-03-04 at 04:18 -0300, Leonardo Bras wrote:
> Humm, this makes sense.
> But with mu change, these pieces of memory only get into ZONE_MOVABLE
> if the boot parameter 'movable_node' gets passed to guest kernel.
Humm, I think your patch also does that.
> So, even if we are unable to so
On Wed, 2020-03-04 at 12:45 -0600, Rob Herring wrote:
> Well, not quite removed yet... Mauro is looking at moving this to ReST,
> but I think it would be better to trim or remove it.
>
> boot-without-of.txt is an ancient document that first outlined
> Flattened DeviceTree. The DT world has evolved
On 5/3/20 7:21 am, Haren Myneni wrote:
On power9, Virtual Accelerator Switchboard (VAS) allows user space or
kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE
instructions. NX provides various functionalities such as compression,
encryption and etc. But only compression
On Wed, Mar 04, 2020 at 04:56:09PM +0100, Cédric Le Goater wrote:
> [ ... ]
>
> > (1) applied the patch which shares the EQ-page with the hypervisor.
> > (2) set "kernel_irqchip=off"
> > (3) set "ic-mode=xive"
>
> you don't have to set the interrupt mode. xive should be negotiated
> by default.
>
On 4/3/20 10:57 am, Michael Ellerman wrote:
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index ef7b1119b2e2..36a8c7b105ce 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -373,7 +373,9 @@ static inline bool flush_coherent_icache(unsigned long addr)
*/
Some specific tests in powerpc can take longer than the default 45
seconds that added in commit 852c8cbf (selftests/kselftest/runner.sh:
Add 45 second timeout per test) to run, the following test result was
collected across 2 Power8 nodes and 1 Power9 node in our pool:
powerpc/benchmarks/futex_be
On 21/2/20 2:27 pm, Alastair D'Silva wrote:
From: Alastair D'Silva
The controller can report a number of statistics that are useful
in evaluating the performance and reliability of the card.
This patch exposes this information via an IOCTL.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/
tly sure what did you mean here, but the kernel has all lockdep
> enabled and did not flag anything here.
As the patch has been dropped from Linux next (next-20200304) perhaps in
order to fold back the __pa_symbol() fix [1], so I am planning to respin
the original patch once more as V15 wh
在 2020/3/5 5:44, Scott Wood 写道:
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
The implementation for Freescale BookE64 is similar as BookE32. One
difference is that Freescale BookE64 set up a TLB mapping of 1G during
booting. Another difference is that ppc64 needs the kernel to be
64K-a
On 21/2/20 2:27 pm, Alastair D'Silva wrote:
From: Alastair D'Silva
These IOCTLs provide low level access to the card to aid in debugging
controller/FPGA firmware.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/platforms/powernv/pmem/Kconfig | 6 +
arch/powerpc/platforms/powernv/pmem/oc
在 2020/3/5 5:49, Scott Wood 写道:
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
The BSS section has already cleared out in the first pass. No need to
clear it again. This can save some time when booting with KASLR
enabled.
Signed-off-by: Jason Yan
Cc: Scott Wood
Cc: Diana Craciun
Cc:
在 2020/3/5 5:53, Scott Wood 写道:
On Thu, 2020-02-06 at 10:58 +0800, Jason Yan wrote:
The original kernel still exists in the memory, clear it now.
Signed-off-by: Jason Yan
Cc: Scott Wood
Cc: Diana Craciun
Cc: Michael Ellerman
Cc: Christophe Leroy
Cc: Benjamin Herrenschmidt
Cc: Paul Mack
在 2020/3/5 5:21, Scott Wood 写道:
On Wed, 2020-02-26 at 18:16 +1100, Daniel Axtens wrote:
Hi Jason,
This is a try to implement KASLR for Freescale BookE64 which is based on
my earlier implementation for Freescale BookE32:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=131718
James Bottomley writes:
> On Wed, 2020-03-04 at 07:35 -0500, Mimi Zohar wrote:
>> On Tue, 2020-03-03 at 23:43 -0800, James Bottomley wrote:
>> > On Tue, 2020-03-03 at 21:33 -0500, Nayna Jain wrote:
>> > > diff --git a/security/integrity/ima/Kconfig
>> > > b/security/integrity/ima/Kconfig
>> > > in
Segher Boessenkool's on March 4, 2020 9:09 am:
> Hi!
>
> On Tue, Mar 03, 2020 at 11:45:27AM +1000, Nicholas Piggin wrote:
>> Provide an option to use ELFv2 ABI for big endian builds. This works on
>> GCC and clang (since 2014). it is is not officially supported by the GNU
>> toolchain, but it can
On 21/2/20 2:27 pm, Alastair D'Silva wrote:
+static int ndctl_smart(struct ocxlpmem *ocxlpmem, struct nd_cmd_pkg *pkg)
+{
+ u32 length, i;
+ struct nd_ocxl_smart *out;
+ int rc;
+
+ mutex_lock(&ocxlpmem->admin_command.lock);
+
+ rc = admin_command_request(ocxlpmem, A
On Tue, 2020-03-03 at 10:28 +0100, Frederic Barrat wrote:
>
> Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > This patch introduces a character device (/dev/ocxl-scmX) which
> > further
> > patches will use to interact with userspace.
> >
> > Signed-off-by:
https://bugzilla.kernel.org/show_bug.cgi?id=206733
--- Comment #3 from Benjamin Herrenschmidt (b...@kernel.crashing.org) ---
Yes. I had a look (and had to swap in some historical brain cells from tape
storage :-) But I think the warning should probably be turned into a dev_dbg.
It's probably some
Michael Ellerman's on March 3, 2020 9:43 pm:
> Nicholas Piggin writes:
>> Use ARCH_HAS_ADDRESS_LOOKUP to look up the opal symbol table. This
>> allows crashes and xmon debugging to print firmware symbols.
>>
>> Oops: System Reset, sig: 6 [#1]
>> LE PAGE_SIZE=64K MMU=Radix SMP NR_CPUS=2048 NUMA
On 4/3/20 7:47 pm, Pingfan Liu wrote:
Splitting out new_property() for coming reusing and moving it to
of_helpers.c.
Also do some coding style cleanup.
Signed-off-by: Pingfan Liu
To: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Hari Ba
On 3/3/20 1:51 AM, Stephane Eranian wrote:
On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra wrote:
On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote:
Modern processors export such hazard data in Performance
Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event
Register' o
On Tue, 2020-03-03 at 11:36 +0100, Frederic Barrat wrote:
>
> Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > The read error log command extracts information from the
> > controller's
> > internal error log.
> >
> > This patch exposes this information in 2 w
Hi Kim,
Sorry about being bit late.
On 3/3/20 3:55 AM, Kim Phillips wrote:
On 3/2/20 2:21 PM, Stephane Eranian wrote:
On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra wrote:
On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote:
Modern processors export such hazard data in Performance
Booting a power9 server with hash MMU could trigger an undefined
behaviour because pud_offset(p4d, 0) will do,
0 >> (PAGE_SHIFT:16 + PTE_INDEX_SIZE:8 + H_PMD_INDEX_SIZE:10)
UBSAN: shift-out-of-bounds in arch/powerpc/mm/ptdump/ptdump.c:282:15
shift exponent 34 is too large for 32-bit type 'int'
Hi Paul,
Sorry for bit late reply.
On 3/3/20 2:38 AM, Paul Clarke wrote:
On 3/1/20 11:23 PM, Ravi Bangoria wrote:
Most modern microprocessors employ complex instruction execution
pipelines such that many instructions can be 'in flight' at any
given point in time. Various factors affect this pi
Hi Andi,
Sorry for being bit late.
On 3/3/20 7:03 AM, Andi Kleen wrote:
On Mon, Mar 02, 2020 at 11:13:32AM +0100, Peter Zijlstra wrote:
On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote:
Modern processors export such hazard data in Performance
Monitoring Unit (PMU) registers. Ex,
exactly sure what did you mean here, but the kernel has all lockdep enabled
and did not flag anything here.
As the patch has been dropped from Linux next (next-20200304) perhaps in
order to fold back the __pa_symbol() fix [1], so I am planning to respin
the original patch once more as V15 while
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
merge
branch HEAD: e3a1ab299346a9a415f334e91a78da7ea84aa5a2 Automatic merge of
branches 'master', 'next' and 'fixes' into merge
elapsed time: 8443m
configs tested: 232
configs skipped: 0
The following configs have
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
next-test
branch HEAD: 55ad7956ff2cfe2c733cea7cf87e9964c56d8c6e cpufreq:powernv: Fix
unsafe notifiers
elapsed time: 8449m
configs tested: 217
configs skipped: 0
The following configs have been built successfully.
Le 05/03/2020 à 05:47, Qian Cai a écrit :
Booting a power9 server with hash MMU could trigger an undefined
behaviour because pud_offset(p4d, 0) will do,
0 >> (PAGE_SHIFT:16 + PTE_INDEX_SIZE:8 + H_PMD_INDEX_SIZE:10)
UBSAN: shift-out-of-bounds in arch/powerpc/mm/ptdump/ptdump.c:282:15
shif
Andrew Donnellan writes:
> On 4/3/20 10:57 am, Michael Ellerman wrote:
>> diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
>> index ef7b1119b2e2..36a8c7b105ce 100644
>> --- a/arch/powerpc/mm/mem.c
>> +++ b/arch/powerpc/mm/mem.c
>> @@ -373,7 +373,9 @@ static inline bool flush_coherent_ica
wrote:
>>>>
>>>> AFAIU, you are not taking an interrupt here. You are stuck in the
>>>> pte_update(), most likely due to nested locks. Try with LOCKDEP ?
>>>
>>> Not exactly sure what did you mean here, but the kernel has all lockdep
>>>
The motivation here is to consolidate VMA flag combinations commonly used
across platforms and reduce code duplication while making it uncluttered
in general.
This first introduces a default VM_DATA_DEFAULT_FLAGS which platforms can
easily fall back on without requiring to define any similar data
There are many platforms with exact same value for VM_DATA_DEFAULT_FLAGS
This creates a default value for VM_DATA_DEFAULT_FLAGS in line with the
existing VM_STACK_DEFAULT_FLAGS. While here, also define some more macros
with standard VMA access flag combinations that are used frequently across
many
There are many places where all basic VMA access flags (read, write, exec)
are initialized or checked against as a group. One such example is during
page fault. Existing vma_is_accessible() wrapper already creates the notion
of VMA accessibility as a group access permissions. Hence lets just create
Christophe Leroy writes:
> Le 05/03/2020 à 05:47, Qian Cai a écrit :
>> Booting a power9 server with hash MMU could trigger an undefined
>> behaviour because pud_offset(p4d, 0) will do,
>>
>> 0 >> (PAGE_SHIFT:16 + PTE_INDEX_SIZE:8 + H_PMD_INDEX_SIZE:10)
>>
>> UBSAN: shift-out-of-bounds in arch
On 3/5/20 12:55 AM, David Gibson wrote:
> On Wed, Mar 04, 2020 at 04:56:09PM +0100, Cédric Le Goater wrote:
>> [ ... ]
>>
>>> (1) applied the patch which shares the EQ-page with the hypervisor.
>>> (2) set "kernel_irqchip=off"
>>> (3) set "ic-mode=xive"
>>
>> you don't have to set the interrupt mod
Po-Hsu Lin writes:
> Some specific tests in powerpc can take longer than the default 45
> seconds that added in commit 852c8cbf (selftests/kselftest/runner.sh:
> Add 45 second timeout per test) to run, the following test result was
> collected across 2 Power8 nodes and 1 Power9 node in our pool:
>
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