On Mon, Feb 24, 2020 at 08:53:25AM +, S.j. Wang wrote:
> Hi
>
> > >
> > > Signed-off-by: Shengjiu Wang
> > > ---
> > > sound/soc/fsl/Kconfig | 10 +
> > > sound/soc/fsl/Makefile |2 +
> > > sound/soc/fsl/fsl_asrc_common.h |1 +
> > > sound/soc/fsl/fsl_easrc.c
It's over 10 years since the last commit from Vitaly, so I suspect
he's moved on to other things.
Christophe has been the primary contributor to 8xx in the last several
years, so anoint him as the maintainer.
Remove the dead penguingppc.org link.
Cc: Vitaly Bordug
Signed-off-by: Michael Ellerma
On 21.02.2020 01:57, Stephen Rothwell wrote:
Hi all,
On Thu, 16 Jan 2020 11:37:14 +1100 Stephen Rothwell
wrote:
On Wed, 15 Jan 2020 14:01:35 -0600 Scott Wood wrote:
On Thu, 2020-01-16 at 06:42 +1100, Stephen Rothwell wrote:
Hi Timur,
On Wed, 15 Jan 2020 07:25:45 -0600 Timur Tabi wro
Hi,
Is there anything else I could do in order to move the changes forward
or is something still missing from this patch set?
Could you please share you mind?
Thanks,
Alexey
On 17.02.2020 11:02, Alexey Budankov wrote:
>
> Currently access to perf_events, i915_perf and other performance
> moni
Le 21/02/2020 à 04:26, Alastair D'Silva a écrit :
From: Alastair D'Silva
This patch adds platform support to map & release LPC memory.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/pnv-ocxl.h | 4 +++
arch/powerpc/platforms/powernv/ocxl.c | 43 +
Gautham R Shenoy wrote:
On Fri, Feb 21, 2020 at 10:50:12AM -0600, Nathan Lynch wrote:
"Gautham R. Shenoy" writes:
> diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
> index 80a676d..5b4b450 100644
> --- a/arch/powerpc/kernel/sysfs.c
> +++ b/arch/powerpc/kernel/sysfs.c
> @@
On Tue, Feb 25, 2020 at 11:51 AM Abdul Haleem
wrote:
>
> On Fri, 2020-01-17 at 18:21 +0530, Abdul Haleem wrote:
> > On Thu, 2020-01-16 at 09:44 -0800, Christoph Hellwig wrote:
> > > Hi Abdul,
> > >
> > > I think the problem is that mpt3sas has some convoluted logic to do
> > > some DMA allocations
Le 21/02/2020 à 04:26, Alastair D'Silva a écrit :
From: Alastair D'Silva
Function declarations don't need externs, remove the existing ones
so they are consistent with newer code
Signed-off-by: Alastair D'Silva
---
Thanks for the cleanup!
Acked-by: Frederic Barrat
arch/powerpc/in
On 2/24/2020 6:18 PM, Gustavo A. R. Silva wrote:
> The current codebase makes use of the zero-length array language
> extension to the C90 standard, but the preferred mechanism to declare
> variable-length types such as these ones is a flexible array member[1][2],
> introduced in C99:
>
> struct f
On 2/25/20 07:44, Horia Geanta wrote:
> On 2/24/2020 6:18 PM, Gustavo A. R. Silva wrote:
>> The current codebase makes use of the zero-length array language
>> extension to the C90 standard, but the preferred mechanism to declare
>> variable-length types such as these ones is a flexible array me
Hello!
On 2/25/20 3:12 PM, Wolfram Sang wrote:
> Adding the Debian-PPC List to reach further people maybe willing to
> test.
This might be related [1].
Adrian
> [1] https://lists.debian.org/debian-powerpc/2020/01/msg00062.html
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer - gl
https://bugzilla.kernel.org/show_bug.cgi?id=201723
Wolfram Sang (w...@the-dreams.de) changed:
What|Removed |Added
Status|NEW |ASSIGNED
--- Comment
https://bugzilla.kernel.org/show_bug.cgi?id=206669
Bug ID: 206669
Summary: Little-endian kernel crashing on POWER8 on heavy
big-endian PowerKVM load
Product: Platform Specific/Hardware
Version: 2.5
Kernel Version: 5.4.x
https://bugzilla.kernel.org/show_bug.cgi?id=199471
Wolfram Sang (w...@the-dreams.de) changed:
What|Removed |Added
CC||w...@the-dreams.de
--
Le 21/02/2020 à 04:26, Alastair D'Silva a écrit :
From: Alastair D'Silva
Tally up the LPC memory on an OpenCAPI link & allow it to be mapped
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/core.c | 10 ++
drivers/misc/ocxl/link.c | 53
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
Add functions to map/unmap LPC memory
Signed-off-by: Alastair D'Silva
---
It looks ok to me.
Acked-by: Frederic Barrat
drivers/misc/ocxl/core.c | 51 +++
drivers/misc/oc
Le 21/02/2020 à 04:27, Alastair D'Silva a écrit :
From: Alastair D'Silva
This patch emits a message showing how much LPC memory & special purpose
memory was detected on an OCXL device.
Signed-off-by: Alastair D'Silva
---
Acked-by: Frederic Barrat
drivers/misc/ocxl/config.c | 4 ++
This is a long overdue update of the series, with fixes from me Michal
and Michael. Does not include Michal's syscall compat series.
Patches 1-22 are changes to low level 64s interrupt entry assembly
which has been posted before, no change except adding patch 21 and
fixing patch 22 to reconcile ir
The code generation macro arguments are difficult to read, and
defaults can't easily be used.
This introduces a block where parameters can be set for interrupt
handler code generation by the subsequent macros, and adds the first
generation macro for interrupt entry.
One interrupt handler is conve
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 1b942c98bc05..f3f2ec8
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index f3f2ec88b3d8..da3c22eea72d 100644
These don't provide a large amount of code sharing. Removing them
makes code easier to shuffle around. For example, some of the common
instructions will be moved into the common code gen macro.
No generated code change.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 1
Aside from label names and BUG line numbers, the generated code change
is an additional HMI KVM handler added for the "late" KVM handler,
because early and late HMI generation is achieved by defining two
different interrupt types.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 68
1 file changed, 30 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 0157ba48efe9..74bf6e0bf61f 100644
--- a/arc
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 55 +---
1 file changed, 26 insertions(+), 29 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 90514766dc7d..cba99f9a815b 100644
--- a/arc
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 51 +---
1 file changed, 24 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 74bf6e0bf61f..90514766dc7d 100644
--- a/arc
Rather than using DAR=2 to select the i-side registers, add an
explicit option.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerp
The real mode interrupt entry points currently use rfid to branch to
the common handler in virtual mode. This is a significant amount of
code, and forces other code (notably the KVM test) to live in the
real mode handler.
In the interest of minimising the amount of code that runs unrelocated
move
As well as moving code out of the unrelocated vectors, this allows the
masked handlers to be moved to common code, and allows the soft_nmi
handler to be generated more like a regular handler.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 106 +-
These are used infrequently enough they don't provide much help, so
inline them.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 82 ++--
1 file changed, 28 insertions(+), 54 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch
Replace IEARLY=1 and IEARLY=2 with IBRANCH_COMMON, which controls if
the entry code branches to a common handler; and IREALMODE_COMMON,
which controls whether the common handler should remain in real mode.
These special cases no longer avoid loading the SRR registers, there
is no point as most of
This allows more code to be moved out of unrelocated regions. The system
call KVMTEST is changed to be open-coded and remain in the tramp area to
avoid having to move it to entry_64.S. The custom nature of the system
call entry code means the hcall case can be made more streamlined than
regular int
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index feb563416abd..7e056488d42a 100644
--- a/arch/powerpc/kernel/exc
The hdec interrupt handler is reported to sometimes fire in Linux if
KVM leaves it pending after a guest exists. This is harmless, so there
is a no-op handler for it.
The interrupt handler currently uses the regular kernel stack. Change
this to avoid touching the stack entirely.
This should be th
The reduction in interrupt entry size allows some handlers to be
re-inlined.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64
Remove more magic numbers and replace with nicely named bools.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 68 +---
1 file changed, 32 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/ex
A few of the non-standard handlers are left uncommented. Some more
description could be added to some.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 391 ---
1 file changed, 353 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/kernel/e
Apart from SRESET, MCE, and syscall (hcall variant), the SRR type
interrupts are not escalated to hypervisor mode, so delivered to the OS.
When running PR KVM, the OS is the hypervisor, and the guest runs with
MSR[PR]=1, so these interrupts must test if a guest was running when
interrupted. These
This adds IRQ_HARD_DIS to irq_happened. Although it doesn't seem to
matter much because we're not allowed to enable irqs in an NMI handler,
the soft-irq debugging code is becoming more strict about ensuring
IRQ_HARD_DIS is in sync with MSR[EE], this may help avoid asserts or
other issues.
Add a co
The soft nmi handler does not reconcile interrupt state, so it should
not return via the normal ret_from_except path. Return like other NMIs,
using the EXCEPTION_RESTORE_REGS macro.
This becomes important when the scv interrupt is implemented, which
must handle soft-masked interrupts that have r13
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame if
they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
onl
Signed-off-by: Nicholas Piggin
---
arch/powerpc/lib/sstep.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index c077acb983a1..5f3a7bd9d90d 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -3179,8
System call entry and particularly exit code is beyond the limit of what
is reasonable to implement in asm.
This conversion moves all conditional branches out of the asm code,
except for the case that all GPRs should be restored at exit.
Null syscall test is about 5% faster after this patch, beca
Kernel addresses and potentially other sensitive data could be leaked
in volatile registers after a syscall.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/entry_64.S | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/en
When local_irq_enable() finds a pending soft-masked interrupt, it
"replays" it by setting up registers like the initial interrupt entry,
then calls into the low level handler to set up an interrupt stack
frame and process the interrupt.
This is not necessary, and uses more stack than needed. The h
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack store.
The stack store emulation is significantly simplfied, rather than creating
a new return frame and switching to that before performing the store, it
uses t
The difference between lite and regular returns is that the lite case
restores all NVGPRs, whereas lite skips that. This is quite clumsy
though, most interrupts want the NVGPRs saved for debugging, not to
modify in the caller, so the NVGPRs restore is not necessary most of
the time. Restore NVGPRs
This reconciles interrupts in the system call case like all other
interrupts. This allows system_call_common to be shared with the
scv system call implementation in a subsequent patch.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/entry_64.S | 11 +++
arch/powerpc/kernel/sysca
The scv instruction causes an interrupt which can enter the kernel with
MSR[EE]=1, thus allowing interrupts to hit at any time. These must not
be taken as normal interrupts, because they come from MSR[PR]=0 context,
and yet the kernel stack is not yet set up and r13 is not set to the
PACA).
Treat
Add support for the scv instruction on POWER9 and later CPUs.
For now this implements the zeroth scv vector 'scv 0', as identical
to 'sc' system calls, with the exception that lr is not preserved, and
it is 64-bit only. There may yet be changes made to this ABI, so it's
for testing only.
rfscv is
Removing attach_adapter from this driver caused a regression for at
least some machines. Those machines had the sensors described in their
DT, too, so they didn't need manual creation of the sensor devices. The
old code worked, though, because manual creation came first. Creation of
DT devices then
The comment had some flaws which are now fixed:
- the prefix is 'MAC' not 'AAPL'
- no kernel coding style and too short length
- 'we do' instead of 'we to'
Signed-off-by: Wolfram Sang
---
drivers/i2c/busses/i2c-powermac.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
dif
On Tue, Feb 25, 2020 at 03:41:22PM +0100, John Paul Adrian Glaubitz wrote:
> Hello!
>
> On 2/25/20 3:12 PM, Wolfram Sang wrote:
> > Adding the Debian-PPC List to reach further people maybe willing to
> > test.
>
> This might be related [1].
IIUC, this is the same as
https://bugzilla.kernel.org/s
Hi Laurentiu,
On Tue, 25 Feb 2020 11:54:17 +0200 Laurentiu Tudor
wrote:
>
> On 21.02.2020 01:57, Stephen Rothwell wrote:
> >
> > On Thu, 16 Jan 2020 11:37:14 +1100 Stephen Rothwell
> > wrote:
> >>
> >> On Wed, 15 Jan 2020 14:01:35 -0600 Scott Wood wrote:
> >>>
> >>> On Thu, 2020-01-16 at
Hi!
On Wed, Feb 26, 2020 at 03:35:35AM +1000, Nicholas Piggin wrote:
> Kernel addresses and potentially other sensitive data could be leaked
> in volatile registers after a syscall.
> cmpdi r3,0
> bne .Lsyscall_restore_regs
> + li r0,0
> + li r4,0
> + li
On 02/20/2020 at 12:48 PM Christophe Leroy wrote:
> Le 20/02/2020 à 18:34, Radu Rendec a écrit :
> > On 02/20/2020 at 11:25 AM Christophe Leroy wrote:
> >> Le 20/02/2020 à 17:02, Radu Rendec a écrit :
> >>> On 02/20/2020 at 3:38 AM Christophe Leroy wrote:
> On 02/19/2020 10:39 PM, Radu Rend
On Mon, 2020-02-24 at 17:51 +1100, Oliver O'Halloran wrote:
> On Mon, Feb 24, 2020 at 3:43 PM Alastair D'Silva <
> alast...@au1.ibm.com> wrote:
> > On Sun, 2020-02-23 at 20:37 -0800, Matthew Wilcox wrote:
> > > On Mon, Feb 24, 2020 at 03:34:07PM +1100, Alastair D'Silva wrote:
> > > > V3:
> > > >
On Tue, 2020-02-25 at 11:02 +0100, Frederic Barrat wrote:
>
> Le 21/02/2020 à 04:26, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > This patch adds platform support to map & release LPC memory.
> >
> > Signed-off-by: Alastair D'Silva
> > ---
> > arch/powerpc/include/asm/pnv-oc
On Tue, 2020-02-25 at 17:30 +0100, Frederic Barrat wrote:
>
> Le 21/02/2020 à 04:26, Alastair D'Silva a écrit :
> > From: Alastair D'Silva
> >
> > Tally up the LPC memory on an OpenCAPI link & allow it to be mapped
> >
> > Signed-off-by: Alastair D'Silva
> > ---
> > drivers/misc/ocxl/core.c
On Tue, Feb 25, 2020 at 4:14 PM Alastair D'Silva wrote:
>
> On Mon, 2020-02-24 at 17:51 +1100, Oliver O'Halloran wrote:
> > On Mon, Feb 24, 2020 at 3:43 PM Alastair D'Silva <
> > alast...@au1.ibm.com> wrote:
> > > On Sun, 2020-02-23 at 20:37 -0800, Matthew Wilcox wrote:
> > > > On Mon, Feb 24, 202
On Tue, 2020-02-25 at 16:32 -0800, Dan Williams wrote:
> On Tue, Feb 25, 2020 at 4:14 PM Alastair D'Silva <
> alast...@au1.ibm.com> wrote:
> > On Mon, 2020-02-24 at 17:51 +1100, Oliver O'Halloran wrote:
> > > On Mon, Feb 24, 2020 at 3:43 PM Alastair D'Silva <
> > > alast...@au1.ibm.com> wrote:
> >
On Tue, Feb 25, 2020 at 4:05 PM Nicolin Chen wrote:
>
> On Mon, Feb 24, 2020 at 08:53:25AM +, S.j. Wang wrote:
> > Hi
> >
> > > >
> > > > Signed-off-by: Shengjiu Wang
> > > > ---
> > > > sound/soc/fsl/Kconfig | 10 +
> > > > sound/soc/fsl/Makefile |2 +
> > > > sound
在 2020/2/20 21:40, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
Some code refactor in kaslr_legal_offset() and kaslr_early_init(). No
functional change. This is a preparation for KASLR fsl_booke64.
Signed-off-by: Jason Yan
Cc: Scott Wood
Cc: Diana Craciun
Cc: Michael
在 2020/2/20 21:48, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
The implementation for Freescale BookE64 is similar as BookE32. One
difference is that Freescale BookE64 set up a TLB mapping of 1G during
booting. Another difference is that ppc64 needs the kernel to be
64K-
在 2020/2/20 21:49, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
The original kernel still exists in the memory, clear it now.
No such problem with PPC32 ? Or is that common ?
PPC32 did this in relocate_init() in fsl_booke.c because PPC32 will not
reach kaslr_early_i
在 2020/2/20 21:50, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
Now we support both 32 and 64 bit KASLR for fsl booke. Add document for
64 bit part and rename kaslr-booke32.rst to kaslr-booke.rst.
Signed-off-by: Jason Yan
Cc: Scott Wood
Cc: Diana Craciun
Cc: Michael E
On Wed, Feb 26, 2020 at 09:51:39AM +0800, Shengjiu Wang wrote:
> > > > > +static const struct regmap_config fsl_easrc_regmap_config = {
> > > > > + .readable_reg = fsl_easrc_readable_reg,
> > > > > + .volatile_reg = fsl_easrc_volatile_reg,
> > > > > + .writeable_reg = fsl_easrc_writeabl
在 2020/2/26 10:40, Jason Yan 写道:
在 2020/2/20 21:48, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
The implementation for Freescale BookE64 is similar as BookE32. One
difference is that Freescale BookE64 set up a TLB mapping of 1G during
booting. Another difference is th
Segher Boessenkool's on February 26, 2020 7:20 am:
> Hi!
>
> On Wed, Feb 26, 2020 at 03:35:35AM +1000, Nicholas Piggin wrote:
>> Kernel addresses and potentially other sensitive data could be leaked
>> in volatile registers after a syscall.
>
>> cmpdi r3,0
>> bne .Lsyscall_restore
bugzilla-dae...@bugzilla.kernel.org's on February 26, 2020 1:26 am:
> https://bugzilla.kernel.org/show_bug.cgi?id=206669
>
> Bug ID: 206669
>Summary: Little-endian kernel crashing on POWER8 on heavy
> big-endian PowerKVM load
>Product: Platfo
https://bugzilla.kernel.org/show_bug.cgi?id=206669
--- Comment #1 from npig...@gmail.com ---
bugzilla-dae...@bugzilla.kernel.org's on February 26, 2020 1:26 am:
> https://bugzilla.kernel.org/show_bug.cgi?id=206669
>
> Bug ID: 206669
>Summary: Little-endian kernel crashing
A future revision of the ISA will introduce prefixed instructions. A
prefixed instruction is composed of a 4-byte prefix followed by a
4-byte suffix.
All prefixes have the major opcode 1. A prefix will never be a valid
word instruction. A suffix may be an existing word instruction or a
new instruc
From: Alistair Popple
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple
---
arch/powerpc/include/asm/reg.h| 3 +++
arch/powerpc/kernel/d
Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
exception is a prefixed instruction that crosses a 64-byte boundary.
Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
instructions.
Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
Currently all instructions are a single word long. A future ISA version
will include prefixed instructions which have a double word length. The
functions used for analysing and emulating instructions need to be
modified so that they can handle these new instruction types.
A prefixed instruction is
This adds emulation support for the following prefixed integer
load/stores:
* Prefixed Load Byte and Zero (plbz)
* Prefixed Load Halfword and Zero (plhz)
* Prefixed Load Halfword Algebraic (plha)
* Prefixed Load Word and Zero (plwz)
* Prefixed Load Word Algebraic (plwa)
* Prefixed Load
This adds emulation support for the following prefixed Fixed-Point
Arithmetic instructions:
* Prefixed Add Immediate (paddi)
Signed-off-by: Jordan Niethe
---
v3: Since we moved the prefixed loads/stores into the load/store switch
statement it no longer makes sense to have paddi in there, so mov
Alignment interrupts can be caused by prefixed instructions accessing
memory. In the alignment handler the instruction that caused the
exception is loaded and attempted emulate. If the instruction is a
prefixed instruction load the prefix and suffix to emulate. After
emulating increment the NIP by
If prefixed instructions are made unavailable by the [H]FSCR, attempting
to use them will cause a facility unavailable exception. Add "PREFIX" to
the facility_strings[].
Currently there are no prefixed instructions that are actually emulated
by emulate_instruction() within facility_unavailable_exc
For modifying instructions in xmon, patch_instruction() can serve the
same role that store_inst() is performing with the advantage of not
being specific to xmon. In some places patch_instruction() is already
being using followed by store_inst(). In these cases just remove the
store_inst(). Otherwis
A prefixed instruction is composed of a word prefix and a word suffix.
It does not make sense to be able to have a breakpoint on the suffix of
a prefixed instruction, so make this impossible.
When leaving xmon_core() we check to see if we are currently at a
breakpoint. If this is the case, the bre
Currently when xmon is dumping instructions it reads a word at a time
and then prints that instruction (either as a hex number or by
disassembling it). For prefixed instructions it would be nice to show
its prefix and suffix as together. Use read_instr() so that if a prefix
is encountered its suffi
A prefixed instruction is composed of a word prefix followed by a word
suffix. It does not make sense to be able to have a kprobe on the suffix
of a prefixed instruction, so make this impossible.
Kprobes work by replacing an instruction with a trap and saving that
instruction to be single stepped
Uprobes can execute instructions out of line. Increase the size of the
buffer used for this so that this works for prefixed instructions. Take
into account the length of prefixed instructions when fixing up the nip.
Signed-off-by: Jordan Niethe
---
v2: - Fix typo
- Use macro for instruction
Currently when getting an instruction to emulate in
hw_breakpoint_handler() we do not load the suffix of a prefixed
instruction. Ensure we load the suffix if the instruction we need to
emulate is a prefixed instruction.
Signed-off-by: Jordan Niethe
---
v2: Rename sufx to suffix
v3: Add __user to
mce_find_instr_ea_and_pfn analyses an instruction to determine the
effective address that caused the machine check. Update this to load and
pass the suffix to analyse_instr for prefixed instructions.
Signed-off-by: Jordan Niethe
---
v2: - Rename sufx to suffix
---
arch/powerpc/kernel/mce_power.c
In ocxl_context_free() we note that the AFU reference we're releasing was
taken in "ocxl_context_init", a function that doesn't actually exist.
Fix it to say ocxl_context_alloc() instead, which I expect was what was
intended.
Fixes: 5ef3166e8a32 ("ocxl: Driver code for 'generic' opencapi devices"
The motivation here is to consolidate VMA flags and helpers in generic
memory header and reduce code duplication when ever applicable. If there
are other possible similar instances which might be missing here, please
do let me me know. I will be happy to incorporate them.
This series is based on v
Idea of a foreign VMA with respect to the present context is very generic.
But currently there are two identical definitions for this in powerpc and
x86 platforms. Lets consolidate those redundant definitions while making
vma_is_foreign() available for general use later. This should not cause
any f
---
This works for me. Only had to leave the #ifdef around the map_mem_in_cams()
Also had to set linear_sz and ram for the alternative case, otherwise I get
arch/powerpc/mm/nohash/kaslr_booke.c: In function 'kaslr_early_init':
arch/powerpc/mm/nohash/kaslr_booke.c:355:33: error: 'linear_sz' may b
On 21/2/20 2:27 pm, Alastair D'Silva wrote:
From: Alastair D'Silva
This driver exposes LPC memory on OpenCAPI pmem cards
as an NVDIMM, allowing the existing nvram infrastructure
to be used.
Namespace metadata is stored on the media itself, so
scm_reserve_metadata() maps 1 section's worth of PM
Le 26/02/2020 à 03:40, Jason Yan a écrit :
在 2020/2/20 21:48, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
/*
* Decide which 64M we want to start
* Only use the low 8 bits of the random seed
*/
- index = random & 0xFF;
+ unsigned long i
Le 26/02/2020 à 04:33, Jason Yan a écrit :
在 2020/2/26 10:40, Jason Yan 写道:
在 2020/2/20 21:48, Christophe Leroy 写道:
Le 06/02/2020 à 03:58, Jason Yan a écrit :
Hi Christophe,
When using a standard C if/else, all code compiled for PPC32 and PPC64,
but this will bring some build error
On Wed, 2020-02-26 at 16:07 +1100, Andrew Donnellan wrote:
> On 21/2/20 2:27 pm, Alastair D'Silva wrote:
> > From: Alastair D'Silva
> >
> > This driver exposes LPC memory on OpenCAPI pmem cards
> > as an NVDIMM, allowing the existing nvram infrastructure
> > to be used.
> >
> > Namespace metadat
Signed-off-by: Nicholas Piggin
---
arch/powerpc/lib/test_emulate_step.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/test_emulate_step.c
b/arch/powerpc/lib/test_emulate_step.c
index 42347067739c..00d70253cb5b 100644
--- a/arch/powerpc/lib/test_emulate_step
From: Christophe Leroy
With CONFIG_STRICT_KERNEL_RWX=y and CONFIG_KPROBES=y, there will be one
W+X page at boot by default. This can be tested with
CONFIG_PPC_PTDUMP=y and CONFIG_PPC_DEBUG_WX=y set, and checking the
kernel log during boot.
powerpc doesn't implement its own alloc() for kprobes l
Picking up from Christophe's last series, including the following changes:
- [6/8] Cast "data" to unsigned long instead of int to fix build
- [8/8] New, to fix an issue reported by Jordan Niethe
Christophe's last series is here:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=15642
From: Christophe Leroy
The set_memory_{ro/rw/nx/x}() functions are required for STRICT_MODULE_RWX,
and are generally useful primitives to have. This implementation is
designed to be completely generic across powerpc's many MMUs.
It's possible that this could be optimised to be faster for specif
Very rudimentary, just
echo 1 > [debugfs]/check_wx_pages
and check the kernel log. Useful for testing strict module RWX.
Updated the Kconfig entry to reflect this.
Also fixed a typo.
Signed-off-by: Russell Currey
---
arch/powerpc/Kconfig.debug | 6 --
arch/powerpc/mm/ptdum
To enable strict module RWX on powerpc, set:
CONFIG_STRICT_MODULE_RWX=y
You should also have CONFIG_STRICT_KERNEL_RWX=y set to have any real
security benefit.
ARCH_HAS_STRICT_MODULE_RWX is set to require ARCH_HAS_STRICT_KERNEL_RWX.
This is due to a quirk in arch/Kconfig and arch/powerpc/Kcon
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