Re: [PATCH v3 2/2] powerpc/pseries/svm: Disable BHRB/EBB/PMU access

On Thu, Jan 09, 2020 at 09:19:57PM -0800, Sukadev Bhattiprolu wrote: > Ultravisor disables some CPU features like BHRB, EBB and PMU in > secure virtual machines (SVMs). Skip accessing those registers > in SVMs to avoid getting a Program Interrupt. It would be useful to have more explanation of the

[RESEND PATCH v2 0/3] Introduce Self-Save API for deep stop states

RESEND Changes: 1. Updated OPAL API numbering for consistency Skiboot patches: https://patchwork.ozlabs.org/patch/1221011/ RFC v1 patches: https://lkml.org/lkml/2019/12/4/193 Changelog RFC v1 --> v2 1. Optimized preference bitmask 2. Addressed comments from Ram Pai Currently the stop-API supports

[RESEND PATCH v2 1/3] powerpc/powernv: Interface to define support and preference for a SPR

Define a bitmask interface to determine support for the Self Restore, Self Save or both. Also define an interface to determine the preference of that SPR to be strictly saved or restored or encapsulated with an order of preference. The preference bitmask is shown as below: ---

[RESEND PATCH v2 2/3] powerpc/powernv: Introduce Self save support

This commit introduces and leverages the Self save API which OPAL now supports. Add the new Self Save OPAL API call in the list of OPAL calls. Implement the self saving of the SPRs based on the support populated while respecting it's preferences. This implementation allows mixing of support for t

[RESEND PATCH v2 3/3] powerpc/powernv: Parse device tree, population of SPR support

Parse the device tree for nodes self-save, self-restore and populate support for the preferred SPRs based what was advertised by the device tree. Signed-off-by: Pratik Rajesh Sampat --- arch/powerpc/platforms/powernv/idle.c | 104 ++ 1 file changed, 104 insertions(+) dif

Re: linux-next: build warning after merge of the bpf-next tree

On Sat, Jan 11, 2020 at 10:31 PM Alexandre Ghiti wrote: > > > On 1/10/20 7:20 PM, Palmer Dabbelt wrote: > > On Fri, 10 Jan 2020 14:28:17 PST (-0800), alexan...@ghiti.fr wrote: > >> Hi guys, > >> > >> On 10/27/19 8:02 PM, Stephen Rothwell wrote: > >>> Hi all, > >>> > >>> On Fri, 18 Oct 2019 10:56:5

[PATCH v2 0/3] Add support for divde[.] and divdeu[.] instruction emulation

Hi All, This patchset adds support to emulate divde, divde., divdeu and divdeu. instructions and testcases for it. Changes in v2: - * Fix review comments from Paul to make divde_dot and divdeu_dot simple by using divde and divdeu, then goto `arith_done` instead of `compute_done`.

[PATCH v2 1/3] powerpc ppc-opcode: add divde, divde_dot, divdeu and divdeu_dot opcodes

include instruction opcodes for divde, divde_dot, divideu and divideu_dot as macros. Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/pow

[PATCH v2 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions

This patch adds emulation support for divde, divdeu instructions, * Divide Doubleword Extended (divde[.]) * Divide Doubleword Extended Unsigned (divdeu[.]) Reviewed-by: Sandipan Das Signed-off-by: Balamuruhan S --- arch/powerpc/lib/sstep.c | 13 - 1 file changed, 12

[PATCH v2 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions

add testcases for divde, divde., divdeu, divdeu. emulated instructions to cover few scenarios, * with same dividend and divisor to have undefine RT for divdeu[.] * with divide by zero to have undefine RT for both divde[.] and divdeu[.] * with negative div

Re: [PATCH 05/18] powerpc sstep: Prepare to support prefixed instructions

On Tue, Nov 26, 2019 at 04:21:28PM +1100, Jordan Niethe wrote: > Currently all instructions are a single word long. A future ISA version > will include prefixed instructions which have a double word length. The > functions used for analysing and emulating instructions need to be > modified so that

Re: [RFC PATCH v2 07/10] lib: vdso: don't use READ_ONCE() in __c_kernel_time()

Le 11/01/2020 à 12:07, Thomas Gleixner a écrit : Christophe Leroy writes: With READ_ONCE() the 64 bits are being read: Without the READ_ONCE() only 32 bits are read. That's the most optimal. Without READ_ONCE() but with a barrier() after the read, we should get the same result but GCC (GC

Re: [RESEND PATCH v2 1/3] powerpc/powernv: Interface to define support and preference for a SPR

On Mon, Jan 13, 2020 at 09:15:07AM +0530, Pratik Rajesh Sampat wrote: > Define a bitmask interface to determine support for the Self Restore, > Self Save or both. > > Also define an interface to determine the preference of that SPR to > be strictly saved or restored or encapsulated with an order o

Re: [RESEND PATCH v2 2/3] powerpc/powernv: Introduce Self save support

On Mon, Jan 13, 2020 at 09:15:08AM +0530, Pratik Rajesh Sampat wrote: > This commit introduces and leverages the Self save API which OPAL now > supports. > > Add the new Self Save OPAL API call in the list of OPAL calls. > Implement the self saving of the SPRs based on the support populated > whil

Re: [RESEND PATCH v2 3/3] powerpc/powernv: Parse device tree, population of SPR support

On Mon, Jan 13, 2020 at 09:15:09AM +0530, Pratik Rajesh Sampat wrote: > Parse the device tree for nodes self-save, self-restore and populate > support for the preferred SPRs based what was advertised by the device > tree. > > Signed-off-by: Pratik Rajesh Sampat > --- > arch/powerpc/platforms/pow