On 11/28/19 8:55 AM, Rasmus Villemoes wrote:
There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC32. This
is yet another attempt.
v5 can be found
here:https://lore.kernel.org/lkml/20191118112324.22725-1-li...@rasmusvillem
On 29/11/2019 20:16, Jens Axboe wrote:
> On 11/29/19 8:14 AM, Christophe Leroy wrote:
Reverting commit 311ae9e159d8 ("io_uring: fix dead-hung for non-iter
fixed rw") clears the failure.
Most likely an #include is missing.
>>>
>>> Huh weird how the build bots didn't catch th
On powerpc with recent versions of binutils, readelf outputs an extra
field when dumping the symbols of an object file. For example:
35: 083896 FUNCLOCAL DEFAULT [: 8] 1
btf_is_struct
The extra "[: 8]" prevents the GLOBAL_SYM_COUNT variable to
be computed correctly a
On 11/30/19 5:42 PM, Linus Torvalds wrote:
[ Only tangentially related to the power parts ]
On Sat, Nov 30, 2019 at 2:41 AM Michael Ellerman wrote:
There's some changes in security/integrity as part of the secure boot work. They
were all either written by or acked/reviewed by Mimi.
-#if
The pull request you sent on Wed, 27 Nov 2019 14:36:16 +0100:
> git://git.kernel.org:/pub/scm/linux/kernel/git/arnd/playground.git
> tags/y2038-cleanups-5.5
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/ceb307474506f888e8f16dab183405ff01dffa08
Thank you!
--
Deet-d
Now the minimum allocation size for a TCE table level is PAGE_SIZE (64k)
as this is the minimum for alloc_pages(). The limit was set in POWER8
where we did not have sparse RAM so we did not need sparse TCE tables.
On POWER9 we have gaps in the phys address space for which using multi
level TCE tabl
This moves code to make the next patches look simpler. In particular:
1. Separate locals declaration as we will be allocating a smaller DMA
window if a TVE1_4GB option (allows a huge DMA windows at 4GB) is enabled;
2. Pass the bypass offset directly to pnv_pci_ioda2_create_table()
as it is the on
Here is an attempt to support bigger DMA space for devices
supporting DMA masks less than 59 bits (GPUs come into mind
first). POWER9 PHBs have an option to map 2 windows at 0
and select a windows based on DMA address being below or above
4GB.
This adds the "iommu=iommu_bypass" kernel parameter an
So far the only option for a big 64big DMA window was a window located
at 0x800... (1<<59) which creates problems for devices
supporting smaller DMA masks.
This exploits a POWER9 PHB option to allow the second DMA window to map
at 0 and advertises it with a 4GB offset to avoid overlap
IODA2 systems (POWER8/9) allow DMA windows at 2 fixed locations - 0 and
0x800...==1<<59, stored in TVT as TVE0/1. PHB4 on POWER9 has
an additional PHB mode to allow mapping both windows at 0 and selecting
one based on IOBA address - accesses below 4GB go via TVE0 and above
4GB - via TVE
Commit a25bd72badfa ("powerpc/mm/radix: Workaround prefetch issue with
KVM") introduced a number of workarounds as coming out of a guest with
the mmu enabled would make the cpu would start running in hypervisor
state with the PID value from the guest. The cpu will then start
prefetching for the hyp
On Monday, 2 December 2019 12:59:49 PM AEDT Alexey Kardashevskiy wrote:
> Here is an attempt to support bigger DMA space for devices
> supporting DMA masks less than 59 bits (GPUs come into mind
> first). POWER9 PHBs have an option to map 2 windows at 0
> and select a windows based on DMA address b
Hi Jan,
Jan Stancek writes:
> - Original Message -
>>
>> Hello,
>>
>> We ran automated tests on a recent commit from this kernel tree:
>>
>>Kernel repo:
>>git://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git
>> Commit: 3b5f97139acc - KVM: PP
We are about to allow another location for the second DMA window and
we will need to advertise it outside of the powernv platform code.
This moves bypass base address to iommu_table_group so drivers such as
VFIO SPAPR TCE can see it.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/
Aurelien Jarno writes:
> On powerpc with recent versions of binutils, readelf outputs an extra
> field when dumping the symbols of an object file. For example:
>
> 35: 083896 FUNCLOCAL DEFAULT [: 8] 1
> btf_is_struct
>
> The extra "[: 8]" prevents the GLOBAL_SYM_COUNT
On 02/12/2019 16:36, Alistair Popple wrote:
> On Monday, 2 December 2019 12:59:49 PM AEDT Alexey Kardashevskiy wrote:
>> Here is an attempt to support bigger DMA space for devices
>> supporting DMA masks less than 59 bits (GPUs come into mind
>> first). POWER9 PHBs have an option to map 2 window
Resource struct p->res is assigned later. Avoid using %pR before the resource
struct is assigned.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/papr_scm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/ar
All other architecture export this as GPL symbol
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/lib/pmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 377712e85605..0666a8d29596 100644
--- a/arch/powerpc/lib/pm
This ensures we don't do a partial mapping of memory. With nvdimm, when creating
namespaces with size not aligned to 16MB, kernel ends up partially mapping the
pages.
This results in a crash when a namespace is removed. This is due to kernel doing
unmap of a page that was part of both the namespac
H_PUT_TCE_INDIRECT hcall uses a page filled with TCE entries, as one of
its parameters. One page is dedicated per cpu, for the lifetime of the
kernel for this purpose. On secure VMs, contents of this page, when
accessed by the hypervisor, retrieves encrypted TCE entries. Hypervisor
needs to know t
This patch series enables IOMMU support for pseries Secure VMs.
Tested using QEMU command line option:
"-device virtio-scsi-pci,id=scsi0,bus=pci.0,addr=0x4,
iommu_platform=on,disable-modern=off,disable-legacy=on"
and
"-device virtio-blk-pci,scsi=off,bus=pci.0,
addr=0x5,drive=
Commit edea902c1c1e ("powerpc/pseries/iommu: Don't use dma_iommu_ops on
secure guests")
disabled dma_iommu_ops path, for secure VMs. The rationale for disabling
the dma_iommu_ops path, was to use the dma_direct path, since it had
inbuilt support for bounce-buffering through SWIOTLB.
This series:
- adds getcpu() on non SMP ppc32
- adds coarse clocks in clock_gettime
- fixes and adds all clocks in clock_getres
- optimises the retrieval of the datapage address
- optimises the cache functions
v4:
- Rebased on top of ceb307474506 ("Merge tag 'y2038-cleanups-5.5' of
git://git.kern
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