I have been hitting EEH address errors testing this with some network
cards which map/unmap DMA addresses more frequently. For example:
PHB4 PHB#5 Diag-data (Version: 1)
Powerpc hw triggers watchpoint before executing the instruction.
To make trigger-after-execute behavior, kernel emulates the
instruction. If the instruction is 'load something into non-
volatile register', exception handler should restore emulated
register state while returning back, otherwise ther
On 6/5/19 11:20 PM, Christoph Hellwig wrote:
On Wed, Jun 05, 2019 at 11:01:17PM -0700, John Hubbard wrote:
I started reviewing this one patch, and it's kind of messy figuring out
if the code motion preserves everything because of
all the consolidation from other places, plus having to move thing
Ravi Bangoria wrote:
Powerpc hw triggers watchpoint before executing the instruction.
To make trigger-after-execute behavior, kernel emulates the
instruction. If the instruction is 'load something into non-
volatile register', exception handler should restore emulated
register state while returni
On 6/6/19 12:59 PM, Ravi Bangoria wrote:
> Powerpc hw triggers watchpoint before executing the instruction.
> To make trigger-after-execute behavior, kernel emulates the
> instruction. If the instruction is 'load something into non-
> volatile register', exception handler should restore emulated
Hi Michael,
On Wed, Jun 5, 2019 at 3:18 PM Andrew Donnellan wrote:
>
> On 4/6/19 10:12 pm, Masahiro Yamada wrote:
> > On Tue, Jun 4, 2019 at 8:54 PM Frederic Barrat
> > wrote:
> >>
> >>
> >>
> >> Le 04/06/2019 à 13:16, Masahiro Yamada a écrit :
> >>> Linux kernel tolerates C++ style comments th
Hi,
On Thu, Jun 06, 2019 at 10:54:51AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2019-06-06 at 01:50 +0300, Aaro Koskinen wrote:
> > Hi,
> >
> > When upgrading from v5.0 -> v5.1 on G4 PowerBook, I noticed WLAN does
> > not work anymore:
> >
> > [ 42.004303] b43legacy-phy0: Loading firmwar
On Thu, 2019-06-06 at 12:31 +0300, Aaro Koskinen wrote:
> Hi,
>
> On Thu, Jun 06, 2019 at 10:54:51AM +1000, Benjamin Herrenschmidt
> wrote:
> > On Thu, 2019-06-06 at 01:50 +0300, Aaro Koskinen wrote:
> > > Hi,
> > >
> > > When upgrading from v5.0 -> v5.1 on G4 PowerBook, I noticed WLAN
> > > does
On Thu, 2019-06-06 at 20:56 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2019-06-06 at 12:31 +0300, Aaro Koskinen wrote:
> > Hi,
> >
> > On Thu, Jun 06, 2019 at 10:54:51AM +1000, Benjamin Herrenschmidt
> > wrote:
> > > On Thu, 2019-06-06 at 01:50 +0300, Aaro Koskinen wrote:
> > > > Hi,
> > > >
commit d84cc9c9524e ("crypto: talitos - fix ECB algs ivsize")
wrongly modified CBC algs ivsize instead of ECB aggs ivsize.
This restore the CBC algs original ivsize of removes ECB's ones.
Signed-off-by: Christophe Leroy
Fixes: d84cc9c9524e ("crypto: talitos - fix ECB algs ivsize")
---
drivers/c
This series is the last set of fixes for the Talitos driver.
We now get a fully clean boot on both SEC1 (SEC1.2 on mpc885) and
SEC2 (SEC2.2 on mpc8321E) with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[3.385197] bus: 'platform': really_probe: probing driver talitos with
device ff02.crypto
[3
Next patch will require struct talitos_edesc to be defined
earlier in talitos.c
This patch moves it into talitos.h so that it can be used
from any place in talitos.c
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on
SEC1")
Signed-off-by: Christophe Leroy
---
drivers/c
When building for SEC1 only, talitos2_done functions are unneeded
and should go away.
For this, use has_ftr_sec1() which will always return true when only
SEC1 support is being built, allowing GCC to drop TALITOS2 functions.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 2 +-
1
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector
6, cfg="random: may_sleep use_f
icv_ool is not used anymore, drop it.
Fixes: 9cc87bc3613b ("crypto: talitos - fix AEAD processing")
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 ---
drivers/crypto/talitos.h | 2 --
2 files changed, 5 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talit
On Thu, Jun 06, 2019 at 08:57:49PM +1000, Benjamin Herrenschmidt wrote:
> > Wow... that's an odd amount. One thing we could possibly do is add code
> > to limit the amount of RAM when we detect that device
>
> Sent too quickly... I mean that *or* force swiotlb at 30-bits on those
> systems ba
On Thu, Jun 6, 2019 at 5:17 PM Alistair Popple wrote:
>
> I have been hitting EEH address errors testing this with some network
> cards which map/unmap DMA addresses more frequently. For example:
>
> PHB4 PHB#5 Diag-data (Version: 1)
> brdgCtl:0002
> RootSts:00060020 00402000 a0220008
Alexey Kardashevskiy writes:
> On 02/06/2019 14:43, Aneesh Kumar K.V wrote:
>> SCM_READ/WRITE_MEATADATA hcall supports multibyte read/write. This patch
>> updates the metadata read/write to use 1, 2, 4 or 8 byte read/write as
>> mentioned in PAPR document.
>>
>> READ/WRITE_METADATA hcall support
Michael Ellerman writes:
> "Aneesh Kumar K.V" writes:
>> Oliver writes:
>>> On Sun, Jun 2, 2019 at 2:44 PM Aneesh Kumar K.V
>>> wrote:
> ...
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.c
index 0176ce66673f..e33cebb8ee6c 10064
On Thu, 2019-06-06 at 07:15 +0200, Christophe Leroy wrote:
>
> Le 05/06/2019 à 23:45, Radu Rendec a écrit :
> > Hi Everyone,
> >
> > I'm seeing some weird memory corruption that I have been able to isolate
> > to arch_ptrace() [arch/powerpc/kernel/ptrace.c] and PTRACE_POKEUSR. I am
> > on PowerPC
Hi ,
can you elobarate this ,meaning which file need to be modified etc .
--
Sent from: http://linuxppc.10917.n7.nabble.com/linuxppc-dev-f3.html
can yo explain little more on this
--
Sent from: http://linuxppc.10917.n7.nabble.com/linuxppc-dev-f3.html
The powerpc's flush_cache_vmap() is defined as a macro and never use
both of its arguments, so it will generate a compilation warning,
lib/ioremap.c: In function 'ioremap_page_range':
lib/ioremap.c:203:16: warning: variable 'start' set but not used
[-Wunused-but-set-variable]
Fix it by making it
Nicholas Piggin writes:
> Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
> in pte helpers") changed the actual bitwise tests in pte_access_permitted
> by using pte_write() and pte_present() helpers rather than raw bitwise
> testing _PAGE_WRITE and _PAGE_PRESENT bits.
>
>
From: Sukadev Bhattiprolu
The ultravisor processor mode is introduced in POWER platforms that
supports the Protected Execution Facility (PEF). Ultravisor is higher
privileged than hypervisor mode.
In PEF enabled platforms, the MSR_S bit is used to indicate if the
thread is in secure state. With
From: Anshuman Khandual
CONFIG_PPC_UV adds support for ultravisor.
Signed-off-by: Anshuman Khandual
Signed-off-by: Bharata B Rao
Signed-off-by: Ram Pai
[Update config help and commit message]
Signed-off-by: Claudio Carvalho
---
arch/powerpc/Kconfig | 20
1 file changed,
This feature tells if the ultravisor firmware is available to handle
ucalls.
Signed-off-by: Claudio Carvalho
[Device node name to "ibm,ultravisor"]
Signed-off-by: Michael Anderson
---
arch/powerpc/include/asm/firmware.h | 5 +++--
arch/powerpc/include/asm/ultravisor.h | 15 +++
a
From: Ram Pai
Add the ucall() function, which can be used to make ultravisor calls
with varied number of in and out arguments. Ultravisor calls can be made
from the host or guests.
This copies the implementation of plpar_hcall().
Signed-off-by: Ram Pai
[Change ucall.S to not save CR, rename an
From: Michael Anderson
When running under an ultravisor, the ultravisor controls the real
partition table and has it in secure memory where the hypervisor can't
access it, and therefore we (the HV) have to do a ucall whenever we want
to update an entry.
The HV still keeps a copy of its view of t
From: Ram Pai
Ultravisor is responsible for flushing the tlb cache, since it manages
the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
available.
Signed-off-by: Ram Pai
Signed-off-by: Claudio Carvalho
---
arch/powerpc/mm/book3s64/pgtable.c | 33 +---
From: Sukadev Bhattiprolu
To enter a secure guest, we have to go through the ultravisor, therefore
we do a ucall when we are entering a secure guest.
This change is needed for any sort of entry to the secure guest from the
hypervisor, whether it is a return from an hcall, a return from a
hypervi
When the ultravisor firmware is available, it takes control over the
LDBAR register. In this case, thread-imc updates and save/restore
operations on the LDBAR register are handled by ultravisor.
Signed-off-by: Claudio Carvalho
Signed-off-by: Ram Pai
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S
POWER platforms that supports the Protected Execution Facility (PEF)
introduce features that combine hardware facilities and firmware to
enable secure virtual machines. That includes a new processor mode
(ultravisor mode) and the ultravisor firmware.
In PEF enabled systems, the ultravisor firmware
From: Michael Anderson
- Check for MSR_S so that kvmppc_set_msr will include. Prior to this
change return to guest would not have the S bit set.
- Patch based on comment from Paul Mackerras
Signed-off-by: Michael Anderson
Signed-off-by: Claudio Carvalho
---
arch/powerpc/kvm/book3s_64_m
On 6/6/19 6:43 AM, Christoph Hellwig wrote:
On Thu, Jun 06, 2019 at 08:57:49PM +1000, Benjamin Herrenschmidt wrote:
Wow... that's an odd amount. One thing we could possibly do is add code
to limit the amount of RAM when we detect that device
Sent too quickly... I mean that *or* force swiot
Claudio Carvalho writes:
> From: Ram Pai
>
> Ultravisor is responsible for flushing the tlb cache, since it manages
> the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> available.
>
> Signed-off-by: Ram Pai
> Signed-off-by: Claudio Carvalho
> ---
> arch/powerpc/mm/book3s6
On 6/6/19 6:43 AM, Christoph Hellwig wrote:
On Thu, Jun 06, 2019 at 08:57:49PM +1000, Benjamin Herrenschmidt wrote:
Wow... that's an odd amount. One thing we could possibly do is add code
to limit the amount of RAM when we detect that device
Sent too quickly... I mean that *or* force swiot
On Thu, Jun 06, 2019 at 04:39:04PM -0300, Murilo Opsfelder Araújo wrote:
> Claudio Carvalho writes:
>
> > From: Ram Pai
> >
> > Ultravisor is responsible for flushing the tlb cache, since it manages
> > the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> > available.
> >
> >
https://bugzilla.kernel.org/show_bug.cgi?id=203837
Bug ID: 203837
Summary: Booting kernel under KVM immediately freezes host
Product: Platform Specific/Hardware
Version: 2.5
Kernel Version: v5.2-rc2
Hardware: PPC-64
OS: Lin
This reverts commit 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645.
ETDR and TX0~5 are TX data registers. There are a couple of reasons
to revert the change:
1) Though ETDR and TX0~5 are not volatile but write-only registers,
they should not be cached either. According to the definition of
"volati
https://bugzilla.kernel.org/show_bug.cgi?id=203839
Bug ID: 203839
Summary: Kernel 5.2-rc3 fails to boot on a PowerMac G4 3,6:
systemd[1]: Failed to bump fs.file-max, ignoring:
invalid argument
Product: Platform Specific/Hard
https://bugzilla.kernel.org/show_bug.cgi?id=203839
--- Comment #1 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 283137
--> https://bugzilla.kernel.org/attachment.cgi?id=283137&action=edit
failed boot, screenshot 5.2-rc1
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You are receiving this mail because:
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https://bugzilla.kernel.org/show_bug.cgi?id=203839
--- Comment #2 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 283139
--> https://bugzilla.kernel.org/attachment.cgi?id=283139&action=edit
kernel .config (5.2-rc3, G4 MDD)
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You are receiving this mail because:
You are watching t
On Thu, 2019-06-06 at 12:59 +0530, Ravi Bangoria wrote:
> Powerpc hw triggers watchpoint before executing the instruction.
> To make trigger-after-execute behavior, kernel emulates the
> instruction. If the instruction is 'load something into non-
> volatile register', exception handler should rest
On Thursday, 6 June 2019 10:07:54 PM AEST Oliver wrote:
> On Thu, Jun 6, 2019 at 5:17 PM Alistair Popple
wrote:
> > I have been hitting EEH address errors testing this with some network
> > cards which map/unmap DMA addresses more frequently. For example:
> >
> > PHB4 PHB#5 Diag-data (Version: 1
On 6/7/19 6:20 AM, Michael Neuling wrote:
> On Thu, 2019-06-06 at 12:59 +0530, Ravi Bangoria wrote:
>> Powerpc hw triggers watchpoint before executing the instruction.
>> To make trigger-after-execute behavior, kernel emulates the
>> instruction. If the instruction is 'load something into non-
>
Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
in pte helpers") changed the actual bitwise tests in pte_access_permitted
by using pte_write() and pte_present() helpers rather than raw bitwise
testing _PAGE_WRITE and _PAGE_PRESENT bits.
The pte_present change now returns t
The change to pmdp_invalidate to mark the pmd with _PAGE_INVALID broke
the synchronisation against lock free lookups, __find_linux_pte's
pmd_none check no longer returns true for such cases.
Fix this by adding a check for this condition as well.
Fixes: da7ad366b497 ("powerpc/mm/book3s: Update pmd
Aneesh Kumar K.V's on June 7, 2019 1:23 am:
> Nicholas Piggin writes:
>
>> Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
>> in pte helpers") changed the actual bitwise tests in pte_access_permitted
>> by using pte_write() and pte_present() helpers rather than raw bitwis
On 06/06/19 11:06 PM, Claudio Carvalho wrote:
When the ultravisor firmware is available, it takes control over the
LDBAR register. In this case, thread-imc updates and save/restore
operations on the LDBAR register are handled by ultravisor.
Signed-off-by: Claudio Carvalho
Signed-off-by: Ram P
During post-migration device tree updates, we can oops in
pseries_update_drconf_memory if the source device tree has an
ibm,dynamic-memory-v2 property and the destination has a
ibm,dynamic_memory (v1) property. The notifier processes an "update"
for the ibm,dynamic-memory property but it's really a
Le 07/06/2019 à 05:56, Nicholas Piggin a écrit :
Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
in pte helpers") changed the actual bitwise tests in pte_access_permitted
by using pte_write() and pte_present() helpers rather than raw bitwise
testing _PAGE_WRITE and _PA
Nicholas Piggin writes:
> Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
> in pte helpers") changed the actual bitwise tests in pte_access_permitted
> by using pte_write() and pte_present() helpers rather than raw bitwise
> testing _PAGE_WRITE and _PAGE_PRESENT bits.
>
>
Le 07/06/2019 à 05:56, Nicholas Piggin a écrit :
The change to pmdp_invalidate to mark the pmd with _PAGE_INVALID broke
the synchronisation against lock free lookups, __find_linux_pte's
pmd_none check no longer returns true for such cases.
Fix this by adding a check for this condition as well
Nicholas Piggin writes:
> The change to pmdp_invalidate to mark the pmd with _PAGE_INVALID broke
> the synchronisation against lock free lookups, __find_linux_pte's
> pmd_none check no longer returns true for such cases.
>
> Fix this by adding a check for this condition as well.
>
Reviewed-by: A
https://bugzilla.kernel.org/show_bug.cgi?id=203837
Paul Mackerras (pau...@ozlabs.org) changed:
What|Removed |Added
CC||pau...@ozlabs.org
--
Ravi Bangoria writes:
> Powerpc hw triggers watchpoint before executing the instruction.
> To make trigger-after-execute behavior, kernel emulates the
> instruction. If the instruction is 'load something into non-
> volatile register', exception handler should restore emulated
> register state wh
On Wed, Jun 5, 2019 at 1:32 PM Mathieu Malaterre wrote:
>
> On Mon, Jun 3, 2019 at 3:00 PM Christophe Leroy
> wrote:
> >
> > When booting through OF, setup_disp_bat() does nothing because
> > disp_BAT are not set. By change, it used to work because BOOTX
> > buffer is mapped 1:1 at address 0x810
This sets the HAVE_ARCH_HUGE_VMAP option, and defines the required
page table functions.
This will not enable huge iomaps, because powerpc/64 ioremap does not
call ioremap_page_range. That is done in a later change.
HAVE_ARCH_HUGE_VMAP facilities will be used to enable huge pages for
vmalloc memo
powerpc/64s does not use ioremap_page_range, so it does not get huge
vmap iomap mappings automatically. The radix kernel mapping function
already allows larger page mappings that work with huge vmap, so wire
that up to allow huge pages to be used for ioremap mappings.
Signed-off-by: Nicholas Piggi
On 6/7/19 11:20 AM, Michael Ellerman wrote:
> Ravi Bangoria writes:
>
>> Powerpc hw triggers watchpoint before executing the instruction.
>> To make trigger-after-execute behavior, kernel emulates the
>> instruction. If the instruction is 'load something into non-
>> volatile register', except
https://bugzilla.kernel.org/show_bug.cgi?id=203837
--- Comment #2 from Paul Mackerras (pau...@ozlabs.org) ---
Just tried 5.1.7 in the host and got the guest locking up during boot. In xmon
I see one cpu in pmdp_invalidate and another in handle_mm_fault. It seems very
possible this is the bug that
Christophe Leroy's on June 7, 2019 3:35 pm:
>
>
> Le 07/06/2019 à 05:56, Nicholas Piggin a écrit :
>> The change to pmdp_invalidate to mark the pmd with _PAGE_INVALID broke
>> the synchronisation against lock free lookups, __find_linux_pte's
>> pmd_none check no longer returns true for such cases
Christophe Leroy's on June 7, 2019 3:34 pm:
>
>
> Le 07/06/2019 à 05:56, Nicholas Piggin a écrit :
>> Commit 1b2443a547f9 ("powerpc/book3s64: Avoid multiple endian conversion
>> in pte helpers") changed the actual bitwise tests in pte_access_permitted
>> by using pte_write() and pte_present() hel
The device tree node is documented as below:
“ibm,cache-flush-required”:
property name indicates Cache Flush Required for this Persistent Memory Segment
to persist memory
prop-encoded-array: None, this is a name only property.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/
SCM_READ/WRITE_MEATADATA hcall supports multibyte read/write. This patch
updates the metadata read/write to use 1, 2, 4 or 8 byte read/write as
mentioned in PAPR document.
READ/WRITE_METADATA hcall supports the 1, 2, 4, or 8 bytes read/write.
For other values hcall results H_P3.
Hypervisor stores
We used uuid_parse to convert uuid string from device tree to two u64
components. We want to make sure we look at the uuid read from device
tree in an endian-neutral fashion. For now, I am picking little-endian
to be format so that we don't end up doing an additional conversion.
The reason to stor
nd_label->dpa issue was observed when trying to enable the namespace created
with little-endian kernel on a big-endian kernel. That made me run
`sparse` on the rest of the code and other changes are the result of that.
Signed-off-by: Aneesh Kumar K.V
---
drivers/nvdimm/btt.c| 8 -
Le 07/06/2019 à 08:19, Nicholas Piggin a écrit :
powerpc/64s does not use ioremap_page_range, so it does not get huge
vmap iomap mappings automatically. The radix kernel mapping function
already allows larger page mappings that work with huge vmap, so wire
that up to allow huge pages to be use
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