Le 13/10/2018 à 00:58, Michael Ellerman a écrit :
If GCC is not built with glibc support then we must explicitly tell it
which register to use for TLS mode stack protector, otherwise it will
error out and the cc-option check will fail.
Oh ? I didn't encounter such a problem with the nolibc G
On 10/13/18 3:23 AM, Kees Cook wrote:
>>
>> $ scripts/get_maintainer.pl --nokeywords --nogit --nogit-fallback
>> include/linux/compat.h
>> linux-ker...@vger.kernel.org (open list)
>
> Normally things like that go through akpm, but I'm happy to carry them
> if needed.
>
Oh okay. Let me try t
On 10/11/2018 02:31 PM, Christophe LEROY wrote:
Le 09/10/2018 à 13:16, Nicholas Piggin a écrit :
On Tue, 9 Oct 2018 09:36:18 +
Christophe Leroy wrote:
On 10/09/2018 05:30 AM, Nicholas Piggin wrote:
On Tue, 9 Oct 2018 06:46:30 +0200
Christophe LEROY wrote:
Le 09/10/2018 à 06:32, Ni
On Sat, 13 Oct 2018 08:29:48 +
Christophe Leroy wrote:
> On 10/11/2018 02:31 PM, Christophe LEROY wrote:
> >
> >
> > Le 09/10/2018 à 13:16, Nicholas Piggin a écrit :
> >> On Tue, 9 Oct 2018 09:36:18 +
> >> Christophe Leroy wrote:
> >>
> >>> On 10/09/2018 05:30 AM, Nicholas Piggin w
Le 13/10/2018 à 10:48, Nicholas Piggin a écrit :
On Sat, 13 Oct 2018 08:29:48 +
Christophe Leroy wrote:
On 10/11/2018 02:31 PM, Christophe LEROY wrote:
Le 09/10/2018 à 13:16, Nicholas Piggin a écrit :
On Tue, 9 Oct 2018 09:36:18 +
Christophe Leroy wrote:
On 10/09/2018 05:30
commit b96672dd840f ("powerpc: Machine check interrupt is a non-
maskable interrupt") added a call to nmi_enter() at the beginning of
machine check restart exception handler. Due to that, in_interrupt()
always returns true regardless of the state before entering the
exception, and die() panics even
commit 06ec27aea9fc ("powerpc/64: add stack protector support")
doesn't initialise the stack canary on SMP secondary CPU's paca,
leading to the following false positive report from the
stack protector.
smp: Bringing up secondary CPUs ...
Kernel panic - not syncing: stack-protector: Kernel stack is
Le 12/10/2018 à 15:23, Abdul Haleem a écrit :
On Fri, 2018-10-12 at 12:36 +0200, Christophe LEROY wrote:
Le 12/10/2018 à 12:31, Abdul Haleem a écrit :
On Fri, 2018-10-12 at 10:08 +0200, Christophe LEROY wrote:
Le 12/10/2018 à 09:48, Abdul Haleem a écrit :
On Fri, 2018-10-12 at 13:15 +053
We use a shared definition for struct pt_regs in uapi/asm/ptrace.h.
That means the layout of the structure is ABI, ie. we can't change it.
That would be fine if it was only used to describe the user-visible
register state of a process, but it's also the struct we use in the
kernel to describe the
Now that we've split the user & kernel versions of pt_regs we need to
be more careful in the ptrace code.
For now we've ensured the location of the fields in both structs is
the same, so most of the ptrace code doesn't need updating.
But there are a few places where we use sizeof(pt_regs), and th
From: Nicholas Piggin
PPR is the odd register out when it comes to interrupt handling, it is
saved in current->thread.ppr while all others are saved on the stack.
The difficulty with this is that accessing thread.ppr can cause a SLB
fault, but the SLB fault handler implementation in C change had
Christophe LEROY writes:
> Le 13/10/2018 à 00:58, Michael Ellerman a écrit :
>> If GCC is not built with glibc support then we must explicitly tell it
>> which register to use for TLS mode stack protector, otherwise it will
>> error out and the cc-option check will fail.
>
> Oh ? I didn't encounte
Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
speific HV idle code to the powernv platform code.
Book3S assembly stubs are kept in common code and used only to save
the stack frame and non-volatile GPRs before executing architected
idle instructions, and restoring the stack a
Dan Williams writes:
> On Tue, Oct 9, 2018 at 11:21 PM Oliver O'Halloran wrote:
>>
>> Adds a driver that implements support for enabling and accessing PAPR
>> SCM regions. Unfortunately due to how the PAPR interface works we can't
>> use the existing of_pmem driver (yet) because:
>>
...
>> +
>> +
On Sat, 13 Oct 2018 21:56:44 +1100
Michael Ellerman wrote:
> We use a shared definition for struct pt_regs in uapi/asm/ptrace.h.
> That means the layout of the structure is ABI, ie. we can't change it.
>
> That would be fine if it was only used to describe the user-visible
> register state of a
On Fri, 2018-10-12 at 21:53 -0700, frowand.l...@gmail.com wrote:
> From: Frank Rowand
>
> Multiple overlay fragments adding or deleting the same node is not
> supported. Replace code comment of such, with check to detect the
> attempt and fail the overlay apply.
>
> Devicetree unittest where mu
From: Nicholas Piggin
This patch moves SLB miss handlers completely to C, using the standard
exception handler macros to set up the stack and branch to C.
This can be done because the segment containing the kernel stack is
always bolted, so accessing it with relocation on will not cause an
SLB e
From: Nicholas Piggin
Add 32-entry bitmaps to track the allocation status of the first 32
SLB entries, and whether they are user or kernel entries. These are
used to allocate free SLB entries first, before resorting to the round
robin allocator.
Signed-off-by: Nicholas Piggin
Signed-off-by: Mic
From: Nicholas Piggin
This will be used by the SLB code in the next patch, but for now this
sets the slb_addr_limit to the correct size for 32-bit tasks.
Signed-off-by: Nicholas Piggin
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 ++
arch/powerpc/incl
From: Nicholas Piggin
When switching processes, currently all user SLBEs are cleared, and a
few (exec_base, pc, and stack) are preloaded. In trivial testing with
small apps, this tends to miss the heap and low 256MB segments, and it
will also miss commonly accessed segments on large memory worklo
From: Nicholas Piggin
slb_flush_and_rebolt() is misleading, it is called in virtual mode, so
it can not possibly change the stack, so it should not be touching the
shadow area. And since vmalloc is no longer bolted, it should not
change any bolted mappings at all.
Change the name to slb_flush_an
From: Nicholas Piggin
This adds CONFIG_DEBUG_VM checks to ensure:
- The kernel stack is in the SLB after it's flushed and bolted.
- We don't insert an SLB for an address that is aleady in the SLB.
- The kernel SLB miss handler does not take an SLB miss.
Signed-off-by: Nicholas Piggin
Sign
There is no good reason to duplicate the PCI menu in every architecture.
Instead provide a selectable HAS_PCI symbol that indicates availability
of PCI support and the handle the rest in drivers/pci.
Note that for powerpc we now select HAS_PCI globally instead of the
convoluted mess of conditional
There is no good reason to duplicate the RAPIDIO menu in various
architectures. Instead provide a selectable HAS_RAPIDIO symbol
that indicates native availability of RAPIDIO support and the handle
the rest in drivers/pci. This also means we now provide support
for PCI(e) to Rapidio bridges for ev
Various powerpc boards select the PCI_MSI config option without selecting
PCI, resulting in potentially not compilable configurations if the by
default enabled PCI option is disabled. Explicitly select PCI to ensure
we always have valid configs.
Signed-off-by: Christoph Hellwig
---
arch/powerpc
There is nothing architecture specific in the PCMCIA core, so allow
building it everywhere. The actual host controllers will depend on ISA,
PCI or a specific SOC.
Signed-off-by: Christoph Hellwig
---
arch/alpha/Kconfig | 2 --
arch/arm/Kconfig | 2 --
arch/ia64/Kconfig | 2 --
ar
Let architectures opt into EISA support by selecting HAS_EISA and
handle everything else in drivers/eisa.
Signed-off-by: Christoph Hellwig
---
arch/alpha/Kconfig | 8 +++-
arch/arm/Kconfig | 16 +---
arch/mips/Kconfig | 31 +--
arch/pow
Signed-off-by: Christoph Hellwig
---
arch/powerpc/Kconfig | 4
drivers/scsi/Kconfig | 6 +++---
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index f0ea460653cd..8b9edf7caf96 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kco
We plan to enable building the pcmcia core and drivers, and the
non-prefixed PCMCIA name clashes with some arch headers.
Signed-off-by: Christoph Hellwig
---
drivers/scsi/aha152x.c | 14 +++---
drivers/scsi/pcmcia/aha152x_core.c | 2 +-
2 files changed, 8 insertions(+), 8 de
The way how CONFIG_PCI_QSPAN selects the CONFIG_PCI default is highly
unusual and gets in the way of moving CONFIG_PCI into
drivers/pci/Kconfig. Simplify it by just having it depend on
CONFIG_PCI.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/Kconfig | 3 +--
1 file changed, 1 insertion(+),
Hi all,
currently every architecture that wants to provide on of the common
periphal busses needs to add some boilerplate code and include the
right Kconfig files. This series instead just selects the presence
(when needed) and then handles everything in the bus-specific
Kconfig file under drive
On Sat, Oct 13, 2018 at 10:55:01PM +1100, Michael Ellerman wrote:
> So it's only my cross compilers that don't work.
>
> The kernel.org ones are:
> Configured with: /home/arnd/git/gcc/configure --target=powerpc64-linux
> --enable-targets=all
> --prefix=/home/arnd/cross/x86_64/gcc-8.1.0-nolib
On Sat, Oct 13, 2018 at 5:08 AM Michael Ellerman wrote:
>
> Dan Williams writes:
> > On Tue, Oct 9, 2018 at 11:21 PM Oliver O'Halloran wrote:
> >>
> >> Adds a driver that implements support for enabling and accessing PAPR
> >> SCM regions. Unfortunately due to how the PAPR interface works we can
WARNING: CPU: 12 PID: 4322 at /arch/powerpc/mm/pgtable-book3s64.c:76
set_pmd_at+0x4c/0x2b0
Modules linked in:
CPU: 12 PID: 4322 Comm: qemu-system-ppc Tainted: GW
4.19.0-rc3-00758-g8f0c636b0542 #36
NIP: c00872fc LR: c0484eec CTR:
REGS: c03
On Fri, Oct 12, 2018 at 07:25:08PM -0700, Daniel Colascione wrote:
[...]
> > But anyway, I think this runtime detection thing is not needed. THP is
> > actually expected to be as fast as this anyway, so if that's available then
> > we should already be as fast.
>
> Ah, I think the commit message
On 10/13/18 05:51, Joe Perches wrote:
> On Fri, 2018-10-12 at 21:53 -0700, frowand.l...@gmail.com wrote:
>> From: Frank Rowand
>>
>> Multiple overlay fragments adding or deleting the same node is not
>> supported. Replace code comment of such, with check to detect the
>> attempt and fail the over
I tried to test the fix to 32-bit poweroc boot hang but found that current git
does not compile on 32bit poweroc at all for me:
CC arch/powerpc/kernel/ptrace.o
In file included from ./include/linux/bitmap.h:9,
from ./include/linux/cpumask.h:12,
from ./inc
The migration of LPARs across Power systems affects many attributes
including that of the associativity of memory blocks. The patches
in this set execute when a system is coming up fresh upon a migration
target. They are intended to,
* Recognize changes to the associativity of memory recorded in
powerpc/drmem: Export many of the functions of DRMEM to parse
"ibm,dynamic-memory" and "ibm,dynamic-memory-v2" during hotplug
operations and for Post Migration events.
Also modify the DRMEM initialization code to allow it to,
* Be called after system initialization
* Provide a separate user copy
powerpc/drmem: Add internal_flags field to each LMB to allow
marking of kernel software-specific operations that need not
be exported to other users. For instance, if information about
selected LMBs needs to be maintained for subsequent passes
through the system, it can be encoded into the LMB arr
migration/memory: This patch adds a new pseries hotplug action
for CPU and memory operations, PSERIES_HP_ELOG_ACTION_READD_MULTIPLE.
This is a variant of the READD operation which performs the action
upon multiple instances of the resource at one time. The operation
is to be triggered by device-tr
migration/memory: This patch adds code that recognizes changes to
the associativity of memory blocks described by the device-tree
properties in order to drive equivalent 'hotplug' operations to
update local and general kernel data structures to reflect those
changes. These differences may include:
migration/memory: This patch adds recognition for changes to the
associativity of memory blocks described by 'ibm,dynamic-memory-v2'.
If the associativity of an LMB has changed, it should be readded to
the system in order to update local and general kernel data structures.
This patch builds upon pr
The PPC mobility code may receive DLPAR CPU add/remove requests
to perform CPU changes at any time, including during LPAR migration
or RTAS requests or SMT changes. When the operations are received
concurrently, there is an opportunity for DLPAR CPU remove requests
and other requests to overlap, a
Christophe Leroy writes:
> Set PAGE_KERNEL directly in the caller and do not rely on a
> hack adding PAGE_KERNEL flags when _PAGE_PRESENT is not set.
>
> As already done for PPC64, use pgprot_cache() helpers instead of
> _PAGE_XXX flags in PPC32 ioremap() derived functions.
>
> Signed-off-by: Chr
>>> The changes were obtained by applying the following Coccinelle script.
How do you think about to adjust the order of provided information
in the commit description?
1. Update goals
2. Transformation implementation at the end
>> "^(?:pte_alloc(?:_one(?:_kernel)?)?|__pte_alloc(?:_kernel)?)$";
From: Lan Tianyu
For nested memory virtualization, Hyper-v doesn't set write-protect
L1 hypervisor EPT page directory and page table node to track changes
while it relies on guest to tell it changes via HvFlushGuestAddressLlist
hypercall. HvFlushGuestAddressLlist hypercall provides a way to flus
From: Lan Tianyu
Add flush range call back in the kvm_x86_ops and platform can use it
to register its associated function. The parameter "kvm_tlb_range"
accepts a single range and flush list which contains a list of ranges.
Signed-off-by: Lan Tianyu
---
Change since v1:
Change "end_gfn"
From: Lan Tianyu
This patch is to add wrapper functions for tlb_remote_flush_with_range
callback.
Signed-off-by: Lan Tianyu
---
Change sicne V3:
Remove code of updating "tlbs_dirty"
Change since V2:
Fix comment in the kvm_flush_remote_tlbs_with_range()
---
arch/x86/kvm/mmu.c | 40
From: Lan Tianyu
This patch is to replace kvm_flush_remote_tlbs() with kvm_flush_
remote_tlbs_with_address() in some functions without logic change.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/mmu.c | 31 +--
arch/x86/kvm/paging_tmpl.h | 3 ++-
2 files chang
From: Lan Tianyu
The patch is to make kvm_set_spte_hva() return int and caller can
check return value to determine flush tlb or not.
Signed-off-by: Lan Tianyu
---
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/mips/include/asm/kvm_host.h| 2 +-
On Sat, Oct 13, 2018 at 05:10:13PM +0200, Christoph Hellwig wrote:
> There is nothing architecture specific in the PCMCIA core, so allow
> building it everywhere. The actual host controllers will depend on ISA,
> PCI or a specific SOC.
>
> Signed-off-by: Christoph Hellwig
Looks good to me, thou
On Saturday 13 October 2018 04:26 PM, Michael Ellerman wrote:
We use a shared definition for struct pt_regs in uapi/asm/ptrace.h.
That means the layout of the structure is ABI, ie. we can't change it.
That would be fine if it was only used to describe the user-visible
register state of a proc
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