On Mon 20-08-18 08:45:10, Alexandre Ghiti wrote:
> Hi Michal,
>
> This patchset got acked, tested and reviewed by quite a few people, and it
> has been suggested
> that it should be included in -mm tree: could you tell me if something else
> needs to be done for
> its inclusion ?
>
> Thanks for y
Ok, my bad, sorry about that, I have just added Andrew as CC then.
Thank you,
Alex
On 08/20/2018 09:17 AM, Michal Hocko wrote:
On Mon 20-08-18 08:45:10, Alexandre Ghiti wrote:
Hi Michal,
This patchset got acked, tested and reviewed by quite a few people, and it
has been suggested
that it sh
On Sun, Aug 19, 2018 at 4:36 PM Lukas Wunner wrote:
>
> Hotplug drivers cannot declare their hotplug_slot_ops const, making them
> attractive targets for attackers, because upon registration of a hotplug
> slot, __pci_hp_initialize() writes to the "owner" and "mod_name" members
> in that struct.
>
On Sun, Aug 19, 2018 at 4:43 PM Lukas Wunner wrote:
>
> Ever since the PCI hotplug core was introduced in 2002, drivers had to
> allocate and register a struct hotplug_slot_info for every slot:
> https://git.kernel.org/tglx/history/c/a8a2069f432c
>
> Apparently the idea was that drivers furnish th
One of the primary issues with Firmware Assisted Dump (fadump) on Power
is that it needs a large amount of memory to be reserved. This reserved
memory is used for saving the contents of old crashed kernel's memory before
fadump capture kernel uses old kernel's memory area to boot. However, This
res
From: Mahesh Salgaonkar
One of the primary issues with Firmware Assisted Dump (fadump) on Power
is that it needs a large amount of memory to be reserved. On large
systems with TeraBytes of memory, this reservation can be quite
significant.
In some cases, fadump fails if the memory reserved is in
On Sun, Aug 19, 2018 at 4:46 PM Lukas Wunner wrote:
>
> When the PCI hotplug core and its first user, cpqphp, were introduced in
> February 2002 with historic commit a8a2069f432c, cpqphp allocated a slot
> struct for its internal use plus a hotplug_slot struct to be registered
> with the hotplug c
From: Mahesh Salgaonkar
fadump fails to register when there are holes in reserved memory area.
This can happen if user has hot-removed a memory that falls in the fadump
reserved memory area. Throw a meaningful error message to the user in
such case.
Signed-off-by: Mahesh Salgaonkar
---
arch/po
From: Mahesh Salgaonkar
For fadump to work successfully there should not be any holes in reserved
memory ranges where kernel has asked firmware to move the content of old
kernel memory in event of crash. Now that fadump uses CMA for reserved
area, this memory area is now not protected from hot-re
On Fri, Aug 17, 2018 at 12:33 PM Arnd Bergmann wrote:
>
> The acpi_pci_create_root_bus() can be fully integrated into
> acpi_pci_root_create(), improving a few things:
>
> * We can call pci_scan_root_bus_bridge(), which registers and
> scans the bridge in one step.
> * After a failure in pci_reg
On Fri, Aug 17, 2018 at 12:32 PM Arnd Bergmann wrote:
>
> pcibios_scan_root() is now just a wrapper around pci_scan_root_bus(),
> and merging the two into one makes it shorter and more readable.
>
> We can also take advantage of pci_alloc_host_bridge() doing the
> allocation of the sysdata for us,
On Sun, Dec 31, 2017 at 08:53:55PM +, Darren Stevens wrote:
> The pasemi smbus controller uses PCI_FUNC(dev->devfn) to define which
> number bus to attach to, however this fails when something else is
> probed first, for example an ATI Radeon graphics card will claim 9 or
> 10 busses, includin
I'd like to rewrite the SLB miss handlers in C for maintainability
and ability to more easily extend the code.
I have not benchmarked it yet but obviously setting up the stack
and going to C code rather than carefully hand optimised assembly
is likely to slow down SLB misses by a reasonable amount
This patch moves SLB miss handlers completely to C, using the standard
exception handler macros to set up the stack and branch to C.
This can be done because the segment containing the kernel stack is
always bolted, so accessing it with relocation on will not cause an
SLB exception.
Arbitrary ker
User SLB mappig data is copied into the PACA from the mm->context
so it can be accessed by the SLB miss handlers.
After the previous patch, SLB miss handlers now run with relocation
on, and user SLB misses are able to take recursive kernel SLB misses,
so the user SLB mapping data can be removed fr
Remove the first vmalloc segment from bolted SLBEs. This is not
required to be bolted, and seems like it was added to help pre-load
the SLB on context switch. However there are now other segments like
the vmemmap segment that often take misses after a context switch, so
it is better to solve this a
Add 32-entry bitmaps to track the allocation status of the first 32
SLB entries, and whether they are user or kernel entries. These are
used to prevent context switches rolling the SLB round robin allocator
and evicting important kernel SLBEs when there are obvious free
entries.
---
arch/powerpc/i
When switching processes, currently all user SLBEs are cleared, and
a few (exec_base, pc, and stack) are preloaded. In trivial testing
with small apps, this tends to miss the heap and low 256MB segments,
and it will also miss commonly accessed segments on large memory
workloads.
Add a simple round
On Mon, 20 Aug 2018 19:41:56 +1000
Nicholas Piggin wrote:
> +long do_slb_fault(struct pt_regs *regs, unsigned long ea)
> +{
> + unsigned long id = REGION_ID(ea);
> +
> + /* IRQs are not reconciled here, so can't check irqs_disabled */
> + VM_WARN_ON(mfmsr() & MSR_EE);
> +
> + /*
On Sun, 19 Aug 2018 22:38:17 +0530
Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> On pseries, as of today system crashes if we get a machine check
> exceptions due to SLB errors. These are soft errors and can be fixed by
> flushing the SLBs so the kernel can continue to function inste
On Mon, Aug 20, 2018 at 10:31 AM Rafael J. Wysocki wrote:
> On Fri, Aug 17, 2018 at 12:32 PM Arnd Bergmann wrote:
> > -static struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
> > - struct pci_ops *ops, void *sysdata, struct list_head
> > *resources)
> > +void pcib
On Mon, Aug 20, 2018 at 10:23 AM Rafael J. Wysocki wrote:
> On Fri, Aug 17, 2018 at 12:33 PM Arnd Bergmann wrote:
> > @@ -909,8 +881,7 @@ struct pci_bus *acpi_pci_root_create(struct
> > acpi_pci_root *root,
> > int ret, busnum = root->secondary.start;
> > struct acpi_device *devi
On Sun, 19 Aug 2018 22:38:32 +0530
Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> If we get a machine check exceptions due to SLB errors then dump the
> current SLB contents which will be very much helpful in debugging the
> root cause of SLB errors. Introduce an exclusive buffer per
On Mon, Aug 20, 2018 at 1:20 PM Arnd Bergmann wrote:
>
> On Mon, Aug 20, 2018 at 10:23 AM Rafael J. Wysocki wrote:
> > On Fri, Aug 17, 2018 at 12:33 PM Arnd Bergmann wrote:
> > > @@ -909,8 +881,7 @@ struct pci_bus *acpi_pci_root_create(struct
> > > acpi_pci_root *root,
> > > int ret, bu
On Mon, Aug 20, 2018 at 1:17 PM Arnd Bergmann wrote:
>
> On Mon, Aug 20, 2018 at 10:31 AM Rafael J. Wysocki wrote:
> > On Fri, Aug 17, 2018 at 12:32 PM Arnd Bergmann wrote:
>
> > > -static struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
> > > - struct pci_ops *ops
On Sun, 19 Aug 2018 22:38:39 +0530
Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> Now that other platforms also implements real mode mce handler,
> lets consolidate the code by sharing existing powernv machine check
> early code. Rename machine_check_powernv_early to
> machine_check_c
On Mon, Aug 20, 2018 at 1:24 PM Rafael J. Wysocki wrote:
>
> On Mon, Aug 20, 2018 at 1:20 PM Arnd Bergmann wrote:
> >
> > On Mon, Aug 20, 2018 at 10:23 AM Rafael J. Wysocki
> > wrote:
> > > On Fri, Aug 17, 2018 at 12:33 PM Arnd Bergmann wrote:
> > > > @@ -909,8 +881,7 @@ struct pci_bus *acpi_p
This feature tells if the hcall H_BLOCK_REMOVE is available.
Cc: "Aneesh Kumar K.V"
Cc: Nicholas Piggin
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Laurent Dufour
---
arch/powerpc/include/asm/firmware.h | 3 ++-
arch
This part of code will be called also when dealing with H_BLOCK_REMOVE.
Cc: "Aneesh Kumar K.V"
Cc: Nicholas Piggin
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Laurent Dufour
---
arch/powerpc/platforms/pseries/lpar.c | 27 +
This hypervisor's call allows to remove up to 8 ptes with only call to
tlbie.
The virtual pages must be all within the same naturally aligned 8 pages
virtual address block and have the same page and segment size encodings.
Cc: "Aneesh Kumar K.V"
Cc: Nicholas Piggin
Cc: Michael Ellerman
Cc: Pau
On very large system we could see soft lockup fired when a process is
exiting
watchdog: BUG: soft lockup - CPU#851 stuck for 21s! [forkoff:215523]
Modules linked in: pseries_rng rng_core xfs raid10 vmx_crypto btrfs libcrc32c
xor zstd_decompress zstd_compress xxhash lzo_compress raid6_pq crc32c_vp
Hello,
I have an odd issue on my powerpc 8xx board.
I am running latest 4.14 and get the following SIGSEGV which appears
more or less randomly.
[9.190354] touch[91]: unhandled signal 11 at 67807b58 nip 777cf114
lr 777cf100 code 30001
[ 24.634810] ifconfig[160]: unhandled signal 11 at 6
On Mon 20-08-18 17:23:58, Christophe LEROY wrote:
> Hello,
>
> I have an odd issue on my powerpc 8xx board.
>
> I am running latest 4.14 and get the following SIGSEGV which appears more or
> less randomly.
>
> [9.190354] touch[91]: unhandled signal 11 at 67807b58 nip 777cf114 lr
> 777cf100 c
Le 20/08/2018 à 18:01, Michal Hocko a écrit :
On Mon 20-08-18 17:23:58, Christophe LEROY wrote:
Hello,
I have an odd issue on my powerpc 8xx board.
I am running latest 4.14 and get the following SIGSEGV which appears more or
less randomly.
[9.190354] touch[91]: unhandled signal 11 at 6
* Gautham R. Shenoy [2018-08-20 11:11:43]:
> From: "Gautham R. Shenoy"
>
> On IBM POWER9, the device tree exposes a property array identifed by
one small nit:
s/identifed/identified/g
> "ibm,thread-groups" which will indicate which groups of threads share
> a particular set of resources.
>
>
* Gautham R. Shenoy [2018-08-20 11:11:44]:
> From: "Gautham R. Shenoy"
>
> Each of the SMT4 cores forming a big-core are more or less independent
> units. Thus when multiple tasks are scheduled to run on the fused
> core, we get the best performance when the tasks are spread across the
> pair o
- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
(Reference design board)
Vabhav Sharma (4):
dt-bindings: ar
Add compatible for LX2160A SoC,QDS and RDB board
Signed-off-by: Vabhav Sharma
---
Documentation/devicetree/bindings/arm/fsl.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
b/Documentation/devicetree/bindings/arm/fsl.txt
index c
Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160
Signed-off-by: Vabhav Sharma
---
drivers/soc/fsl/guts.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..5e1e633 100644
--- a/drivers/soc/fsl/guts.c
+++
From: Yogesh Gaur
Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
As LX2160A is 16 core, so modified value for NUM_CMUX
Signed-off-by: Tang Yuantian
Signed-off-by: Yogesh Gaur
Signed-off-by: Vabhav Sharma
---
drivers/clk/clk-qoriq.c | 14 +
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.
Sig
LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.
Signed-off-by: Priyanka Jain
Signed-off-by: Sriram Dash
Signed-off-by: Vabhav Sharma
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/fr
On 08/19/2018 07:29 AM, Lukas Wunner wrote:
> Hotplug drivers cannot declare their hotplug_slot_ops const, making them
> attractive targets for attackers, because upon registration of a hotplug
> slot, __pci_hp_initialize() writes to the "owner" and "mod_name" members
> in that struct.
>
> Fix by
On 08/19/2018 07:29 AM, Lukas Wunner wrote:
> Ever since the PCI hotplug core was introduced in 2002, drivers had to
> allocate and register a struct hotplug_slot_info for every slot:
> https://git.kernel.org/tglx/history/c/a8a2069f432c
>
> Apparently the idea was that drivers furnish the hotplug
On 08/19/2018 07:29 AM, Lukas Wunner wrote:
> When the PCI hotplug core and its first user, cpqphp, were introduced in
> February 2002 with historic commit a8a2069f432c, cpqphp allocated a slot
> struct for its internal use plus a hotplug_slot struct to be registered
> with the hotplug core and lin
From: Anton Blanchard
Commit 15a3204d24a3 ("powerpc/64s: Set assembler machine type to POWER4")
passes -mpower4 to the assembler. We have more recent instructions in our
assembly files, but gas permits them. The clang/llvm integrated assembler
is more strict, and we get a build failure.
Fix this
From: Anton Blanchard
Static branch hints override dynamic branch prediction on recent
POWER CPUs. We should only use them when we are overwhelmingly
sure of the direction.
Signed-off-by: Anton Blanchard
---
arch/powerpc/lib/mem_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
Adding myself as maintiner of the IBM RPA hotplug modules located in
drivers/pci/hotplug directory. These modules provide kernel interfaces
for support of Dynamic Logical Partitioning (DLPAR) of Logical and
Physical IO slots, and hotplug of physical PCI slots of a PHB on
RPA-compliant ppc64 platfor
Deciding wich govenors should be built into the kernel can be left to
users to configure.
Fixes: 81f359027a3a ("cpufreq: powernv: Select CPUFreq related Kconfig options
for powernv")
Signed-off-by: Joel Stanley
---
arch/powerpc/platforms/powernv/Kconfig | 5 -
1 file changed, 5 deletions(-)
On Tue, 2018-08-21 at 11:44 +0930, Joel Stanley wrote:
> Deciding wich govenors should be built into the kernel can be left to
> users to configure.
>
> Fixes: 81f359027a3a ("cpufreq: powernv: Select CPUFreq related Kconfig
> options for powernv")
> Signed-off-by: Joel Stanley
Can you add them
This patch moves SLB miss handlers completely to C, using the standard
exception handler macros to set up the stack and branch to C.
This can be done because the segment containing the kernel stack is
always bolted, so accessing it with relocation on will not cause an
SLB exception.
Arbitrary ker
Anton Blanchard writes:
> From: Anton Blanchard
>
> Commit 15a3204d24a3 ("powerpc/64s: Set assembler machine type to POWER4")
> passes -mpower4 to the assembler. We have more recent instructions in our
> assembly files, but gas permits them. The clang/llvm integrated assembler
> is more strict,
Hi Michael,
> This breaks GCC 4.6.3 at least, which we still support:
>
> Assembler messages:
> Error: invalid switch -mpower8
> Error: unrecognized option -mpower8
> ../scripts/mod/empty.c:1:0: fatal error: error closing -: Broken
> pipe
Yuck. We have POWER8 instructions in our assembly
On Tue, 2018-08-21 at 15:13 +1000, Nicholas Piggin wrote:
> This patch moves SLB miss handlers completely to C, using the standard
> exception handler macros to set up the stack and branch to C.
>
> This can be done because the segment containing the kernel stack is
> always bolted, so accessing i
On Tue, 21 Aug 2018 15:38:39 +1000
Anton Blanchard wrote:
> Hi Michael,
>
> > This breaks GCC 4.6.3 at least, which we still support:
> >
> > Assembler messages:
> > Error: invalid switch -mpower8
> > Error: unrecognized option -mpower8
> > ../scripts/mod/empty.c:1:0: fatal error: error
Christophe Leroy writes:
> When two processes crash at the same time, we sometimes encounter
> nesting in the middle of a line:
I think "interleaved" is the right word, rather than "nesting".
They're actually (potentially) completely unrelated segfaults, that just
happen to occur at the same ti
Breno Leitao writes:
> On 08/16/2018 09:49 PM, Michael Ellerman wrote:
>> Michael Neuling writes:
>>
>>> On Mon, 2018-06-18 at 19:59 -0300, Breno Leitao wrote:
Currently msr_tm_active() is a wrapper around MSR_TM_ACTIVE() if
CONFIG_PPC_TRANSACTIONAL_MEM is set, or it is just a function
On Fri, Aug 17, 2018 at 12:26:30PM +0200, Arnd Bergmann wrote:
> Hi Bjorn and others,
>
> Triggered by Christoph's patches, I had another go at converting
> all of the remaining pci host bridge implementations to be based
> on pci_alloc_host_bridge and a separate registration function.
I really l
Christophe LEROY writes:
...
>
> And I bisected its disappearance with commit 99cd1302327a2 ("powerpc:
> Deliver SEGV signal on pkey violation")
Whoa that's weird.
> Looking at those two commits, especially the one which makes it
> dissapear, I'm quite sceptic. Any idea on what could be the ca
Nicholas Piggin writes:
> This patch moves SLB miss handlers completely to C, using the standard
> exception handler macros to set up the stack and branch to C.
>
> This can be done because the segment containing the kernel stack is
> always bolted, so accessing it with relocation on will not cau
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