If a device without a driver is recovered via EEH, the flag
EEH_DEV_NO_HANDLER is incorrectly left set on the device after
recovery, because the test in eeh_report_resume() for the existence of
a bound driver is done before the flag is cleared. If a driver is
later bound, and EEH experienced again,
The EEH report functions now share a fair bit of code around the start
and end of each function.
So factor out as much as possible, and move the traversal into a
custom function. This also allows accurate debug to be generated more
easily.
Signed-off-by: Sam Bobroff
---
arch/powerpc/kernel/eeh_
On Wed, May 02, 2018 at 02:07:21PM +1000, Alexey Kardashevskiy wrote:
> This is to allow the guest to use big host IOMMU pages even when
> the exact page size (i.e. 16MB) is not supported by the host
> (i.e.P9).
Thanks for implementing this, it will make a bunch of things rather easier.
>
>
> P
On Wed, May 02, 2018 at 02:07:23PM +1000, Alexey Kardashevskiy wrote:
> At the moment we only support in the host the IOMMU page sizes which
> the guest is aware of, which is 4KB/64KB/16MB. However P9 does not support
> 16MB IOMMU pages, 2MB and 1GB pages are supported instead. We can still
> emula
On Wed, May 02, 2018 at 02:07:22PM +1000, Alexey Kardashevskiy wrote:
> The other TCE handlers use page shift from the guest visible TCE table
> (described by kvmppc_spapr_tce_iommu_table) so let's make H_STUFF_TCE
> handlers do the same thing.
>
> This should cause no behavioral change now but so
Hi Punit,
Thanks for reviewing this series.
On 30/04/2018 20:47, Punit Agrawal wrote:
> Hi Laurent,
>
> One nitpick below.
>
> On Tue, Apr 17, 2018 at 3:33 PM, Laurent Dufour
> wrote:
>> This change is inspired by the Peter's proposal patch [1] which was
>> protecting the VMA using SRCU. Unfor
In commit 4e26bc4a4ed6 ("powerpc/64: Rename soft_enabled to
irq_soft_mask") we renamed paca->soft_enabled. But then in commit
8e0b634b1327 ("powerpc/64s: Do not allocate lppaca if we are not
virtualized") we added it back. Oops. This happened because the two
patches were in flight at the same time
On Wed, May 02, 2018 at 04:26:04PM +1000, Alexey Kardashevskiy wrote:
> On 2/5/18 3:53 pm, Balbir Singh wrote:
> > On Wed, 2 May 2018 14:07:23 +1000
> > Alexey Kardashevskiy wrote:
[snip]
> >> + unsigned long subpg;
> >
> > Why not just i?
>
> I can imagine pages so huge so backing them with 4
2018-03-29 15:50 GMT+08:00 Laurent Dufour :
> On 29/03/2018 05:06, Ganesh Mahendran wrote:
>> 2018-03-29 10:26 GMT+08:00 Ganesh Mahendran :
>>> Hi, Laurent
>>>
>>> 2018-02-16 23:25 GMT+08:00 Laurent Dufour :
When the speculative page fault handler is returning VM_RETRY, there is a
chance
Hi Michael,
On 04/27/2018 09:14 AM, Michael Ellerman wrote:
> laurentiu.tu...@nxp.com writes:
>> From: Laurentiu Tudor
>>
>> Add missing "altivec unavailable" interrupt injection helper
>> thus fixing the linker error below:
>>
>> arch/powerpc/kvm/emulate_loadstore.o: In function
>> `kvmppc_chec
On Tue, 01 May 2018 23:07:28 +1000
Balbir Singh wrote:
> On Tue, 2018-05-01 at 12:22 +1000, Nicholas Piggin wrote:
> > Provide timebase and timebase of last heartbeat in watchdog lockup
> > messages. Also provide a stack trace of when a CPU becomes un-stuck,
> > which can be useful -- it could be
On Wed, May 2, 2018 at 6:38 PM, Nicholas Piggin wrote:
> On Tue, 01 May 2018 23:07:28 +1000
> Balbir Singh wrote:
>
>> On Tue, 2018-05-01 at 12:22 +1000, Nicholas Piggin wrote:
>> > Provide timebase and timebase of last heartbeat in watchdog lockup
>> > messages. Also provide a stack trace of whe
On Wed, May 2, 2018 at 4:26 PM, Alexey Kardashevskiy wrote:
> On 2/5/18 3:53 pm, Balbir Singh wrote:
>> On Wed, 2 May 2018 14:07:23 +1000
>> Alexey Kardashevskiy wrote:
>>
>>> At the moment we only support in the host the IOMMU page sizes which
>>> the guest is aware of, which is 4KB/64KB/16MB.
On 2/5/18 3:49 pm, David Gibson wrote:
> On Wed, May 02, 2018 at 02:07:23PM +1000, Alexey Kardashevskiy wrote:
>> At the moment we only support in the host the IOMMU page sizes which
>> the guest is aware of, which is 4KB/64KB/16MB. However P9 does not support
>> 16MB IOMMU pages, 2MB and 1GB pages
On 2/5/18 6:59 pm, Balbir Singh wrote:
>>>
+unsigned long subpg;
>>>
>>> Why not just i?
>>
>> I can imagine pages so huge so backing them with 4K will overflow 32bit
>> anyway. It is very (very) unlikely but it is 64bit arch anyway and there is
>> no much point in not-long types anyway.
Hi Nipun,
On 04/30/2018 09:27 AM, Nipun Gupta wrote:
> fsl-mc bus support the new iommu-map property. Comply to this binding
> for fsl_mc bus.
>
> Signed-off-by: Nipun Gupta
This looks good to me, so:
Reviewed-By: Laurentiu Tudor
---
Best Regards, Laurentiu
> ---
> arch/arm64/boot/dts/free
Nick,
On Sat, Apr 21, 2018 at 4:48 AM, Nicholas Piggin wrote:
> On Fri, 20 Apr 2018 22:08:27 +0200
> Mathieu Malaterre wrote:
>
>> On Fri, Apr 20, 2018 at 12:41 PM, Nicholas Piggin wrote:
>> > On Fri, 20 Apr 2018 12:00:49 +0200
>> > Mathieu Malaterre wrote:
>> >
>> >> On Fri, Apr 20, 2018 at 9
Hi Nipun,
On 04/30/2018 09:27 AM, Nipun Gupta wrote:
> Signed-off-by: Nipun Gupta
> ---
If my understanding is correct, the kbuild error is triggered by this
missing dependency patch:
https://patchwork.kernel.org/patch/10370081/
Apart from that, patch looks good to me, so
Reviewed-by: Lauren
config TRACING_SUPPORT has an exception for PPC32, because PPC32
didn't have irqflags tracing support.
But that hasn't been true since commit 5d38902c4838 ("powerpc: Add
irqtrace support for 32-bit powerpc") (Jun 2009).
So remove the exception for PPC32 and the comment.
Signed-off-by: Michael El
On Tue, 01 May 2018 21:11:06 +1000
Michael Ellerman wrote:
> Michal Suchánek writes:
> > Hello,
> >
> > On Tue, 24 Apr 2018 14:15:57 +1000
> > Michael Ellerman wrote:
> >
> >> From: Michal Suchanek
> >>
> >> Check what firmware told us and enable/disable the barrier_nospec
> >> as appropria
On Wed, 2 May 2018 11:17:52 +0200
Mathieu Malaterre wrote:
> Nick,
>
> On Sat, Apr 21, 2018 at 4:48 AM, Nicholas Piggin wrote:
> > On Fri, 20 Apr 2018 22:08:27 +0200
> > Mathieu Malaterre wrote:
> >
> >> On Fri, Apr 20, 2018 at 12:41 PM, Nicholas Piggin
> >> wrote:
> >> > On Fri, 20 Apr
On Wed, May 2, 2018 at 6:57 AM, Dan Williams wrote:
> On Thu, Apr 5, 2018 at 8:00 AM, Dan Williams wrote:
>> On Wed, Apr 4, 2018 at 11:45 PM, Nicholas Piggin wrote:
> [,,]
>>> What's the problem with just counting bytes copied like usercopy --
>>> why is that harder than cacheline accuracy?
>>>
On 05/01/2018 07:04 AM, Sam Bobroff wrote:
> From: Sam Bobroff
>
> It is not currently possible to create the full number of possible
> VCPUs (KVM_MAX_VCPUS) on Power9 with KVM-HV when the guest uses less
> threads per core than it's core stride (or "VSMT mode"). This is
> because the VCORE ID an
On Wed, 2 May 2018 21:29:48 +1000
Michael Ellerman wrote:
> config TRACING_SUPPORT has an exception for PPC32, because PPC32
> didn't have irqflags tracing support.
>
> But that hasn't been true since commit 5d38902c4838 ("powerpc: Add
> irqtrace support for 32-bit powerpc") (Jun 2009).
>
> So
A CPU that gets stuck with interrupts hard disable can be difficult to
debug, as on some platforms we have no way to interrupt the CPU to
find out what it's doing.
A stop-gap is to have the CPU save it's stack pointer (r1) in its paca
when it hard disables interrupts. That way if we can't interrup
Currently the options we have for sending NMIs are not necessarily
safe, that is they can potentially interrupt a CPU in a
non-recoverable region of code, meaning the kernel must then panic().
But we'd like to use smp_send_nmi_ipi() to do cross-CPU calls in
situations where we don't want to risk a
This allows eg. the RCU stall detector, or the soft/hardlockup
detectors to trigger a backtrace on all CPUs.
We implement this by sending a "safe" NMI, which will actually only
send an IPI. Unfortunately the generic code prints "NMI", so that's a
little confusing but we can probably live with it.
This now has new code in it written by Nick and I, and switch to a
SPDX tag.
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/stacktrace.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
in
Alexey Kardashevskiy writes:
> At the moment we assume that IODA2 and newer PHBs can always do 4K/64K/16M
> IOMMU pages, however this is not the case for POWER9 and now skiboot
> advertises the supported sizes via the device so we use that instead
> of hard coding the mask.
>
> This falls back to
From: Al Viro
Signed-off-by: Al Viro
---
arch/powerpc/kernel/pci_32.c | 6 +++---
arch/powerpc/kernel/pci_64.c | 4 ++--
arch/powerpc/mm/subpage-prot.c | 4 +++-
arch/powerpc/platforms/cell/spu_syscalls.c | 3 ++-
4 files changed, 10 insertions(+), 7 dele
From: Al Viro
Signed-off-by: Al Viro
[mpe: Fix sys_debug_setcontext() prototype to return long]
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/asm-prototypes.h | 14 ---
arch/powerpc/kernel/signal.h | 6 ++---
arch/powerpc/kernel/signal_32.c | 40 +
From: Al Viro
Signed-off-by: Al Viro
[mpe: Update sys_ni.c for s/ppc_rtas/sys_rtas/]
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/syscalls.h | 2 +-
arch/powerpc/include/asm/systbl.h | 2 +-
arch/powerpc/kernel/rtas.c | 3 ++-
arch/powerpc/ker
Currently the select system call is wired up with the SYSX_SPU()
macro. The SYSX_SPU() is not handled by systbl_chk.c, which means the
syscall number for select is not checked.
That hides the fact that the syscall number for select is actually
__NR__newselect not __NR_select.
In a following patch
From: Al Viro
it had always been pointless - compat_sys_select() sign-extends
the first argument just fine on its own.
Signed-off-by: Al Viro
[mpe: Use COMPAT_SPU_NEW() to keep systbl_chk.sh happy]
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/systbl.h | 2 +-
arch/powerpc/kern
From: Al Viro
Signed-off-by: Al Viro
---
arch/powerpc/include/asm/systbl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/systbl.h
b/arch/powerpc/include/asm/systbl.h
index cdf528089a63..79a3b47e4839 100644
--- a/arch/powerpc/include/asm/systbl.h
+
On 02/05/2018 16:17, Punit Agrawal wrote:
> Hi Laurent,
>
> One query below -
>
> Laurent Dufour writes:
>
> [...]
>
>>
>> Ebizzy:
>> ---
>> The test is counting the number of records per second it can manage, the
>> higher is the best. I run it like this 'ebizzy -mTRp'. To get consisten
Hi Laurent,
One query below -
Laurent Dufour writes:
[...]
>
> Ebizzy:
> ---
> The test is counting the number of records per second it can manage, the
> higher is the best. I run it like this 'ebizzy -mTRp'. To get consistent
> result I repeated the test 100 times and measure the average
Hi Laurent,
Thanks for your reply.
Laurent Dufour writes:
> On 02/05/2018 16:17, Punit Agrawal wrote:
>> Hi Laurent,
>>
>> One query below -
>>
>> Laurent Dufour writes:
>>
>> [...]
>>
>>>
>>> Ebizzy:
>>> ---
>>> The test is counting the number of records per second it can manage, the
On Wed, May 02, 2018 at 09:18:11PM +, Andy Lutomirski wrote:
> On Wed, May 2, 2018 at 2:13 PM Ram Pai wrote:
>
>
> > > Ram, would you please comment?
>
> > on POWER the pkey behavior will remain the same at entry or at exit from
> > the signal handler. For eg: if a key is read-disabled on
On Wed, 2018-05-02 at 16:12 +1000, Alexey Kardashevskiy wrote:
> At the moment we assume that IODA2 and newer PHBs can always do
> 4K/64K/16M
> IOMMU pages, however this is not the case for POWER9 and now skiboot
> advertises the supported sizes via the device so we use that instead
> of hard codin
On Tue, May 01, 2018 at 02:52:21PM +1000, Sam Bobroff wrote:
> On Tue, Apr 24, 2018 at 01:48:25PM +1000, David Gibson wrote:
> > On Tue, Apr 24, 2018 at 01:19:15PM +1000, Sam Bobroff wrote:
> > > On Mon, Apr 23, 2018 at 11:06:35AM +0200, Cédric Le Goater wrote:
> > > > On 04/16/2018 06:09 AM, David
On Tue, May 01, 2018 at 03:04:41PM +1000, Sam Bobroff wrote:
> From: Sam Bobroff
>
> It is not currently possible to create the full number of possible
> VCPUs (KVM_MAX_VCPUS) on Power9 with KVM-HV when the guest uses less
> threads per core than it's core stride (or "VSMT mode"). This is
> becau
On Monday 09 April 2018 02:30 PM, Anju T Sudhakar wrote:
Enable thread-imc in the kernel, only if core-imc is registered.
Can you add more info here? Why we need this and so on.
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/include/asm/imc-pmu.h| 1 +
arch/powerpc/perf/imc-pm
On Monday 09 April 2018 02:30 PM, Anju T Sudhakar wrote:
Return proper error code for unknown domain during IMC initialization.
Looks good to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/perf/imc-pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 d
On Monday 09 April 2018 02:30 PM, Anju T Sudhakar wrote:
Replace the direct return statement in imc_mem_init() with goto,
to adhere to the kernel coding style.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/perf/imc-pmu.c | 18 ++
1 fil
On Monday 09 April 2018 02:30 PM, Anju T Sudhakar wrote:
When any of the IMC (In-Memory Collection counter) devices fail
to initialize, imc_common_mem_free() frees set of memory. In doing so,
pmu_ptr pointer is also freed. But pmu_ptr pointer is used in subsequent
function (imc_common_cpuhp_mem
On Thu, May 03, 2018 at 01:11:13PM +1000, David Gibson wrote:
> On Tue, May 01, 2018 at 02:52:21PM +1000, Sam Bobroff wrote:
> > On Tue, Apr 24, 2018 at 01:48:25PM +1000, David Gibson wrote:
> > > On Tue, Apr 24, 2018 at 01:19:15PM +1000, Sam Bobroff wrote:
> > > > On Mon, Apr 23, 2018 at 11:06:35A
At the moment we assume that IODA2 and newer PHBs can always do 4K/64K/16M
IOMMU pages, however this is not the case for POWER9 and now skiboot
advertises the supported sizes via the device so we use that instead
of hard coding the mask.
Signed-off-by: Alexey Kardashevskiy
---
Changes:
v2:
* adde
On Wed, Apr 25, 2018 at 07:54:38PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> To optimize kvm emulation code with analyse_instr, adds new
> mmio_update_ra flag to aid with GPR RA update.
>
> This patch arms RA update at load/store emulation path for both
> qemu mmio emulation or
On Wed, Apr 25, 2018 at 07:54:43PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> This patch reconstructs LOAD_VMX/STORE_VMX instruction MMIO emulation with
> analyse_intr() input. When emulating the store, the VMX reg will need to
> be flushed so that the right reg val can be retrie
On Wed, Apr 25, 2018 at 07:54:44PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> This patch reconstructs LOAD_VSX/STORE_VSX instruction MMIO emulation with
> analyse_intr() input. It utilizes VSX_FPCONV/VSX_SPLAT/SIGNEXT exported
> by analyse_instr() and handle accordingly.
>
> Whe
On Wed, Apr 25, 2018 at 07:54:42PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> This patch reconstructs LOAD_FP/STORE_FP instruction MMIO emulation with
> analyse_intr() input. It utilizes the FPCONV/UPDATE properties exported by
> analyse_instr() and invokes kvmppc_handle_load(s)/
On Wed, Apr 25, 2018 at 07:54:35PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> This patch moves nip/ctr/lr/xer registers from scattered places in
> kvm_vcpu_arch to pt_regs structure.
>
> cr register is "unsigned long" in pt_regs and u32 in vcpu->arch.
> It will need more conside
On Wed, Apr 25, 2018 at 07:54:34PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> Current regs are scattered at kvm_vcpu_arch structure and it will
> be more neat to organize them into pt_regs structure.
>
> Also it will enable reconstruct MMIO emulation code with
"reimplement" wou
On Wed, Apr 25, 2018 at 07:54:36PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data() to
> retrieve VMX reg val. kvmppc_get_vmx_data() will check mmio_host_swabbed
> to decide which double word of vr[] to be used. But the
On Wed, Apr 25, 2018 at 07:54:40PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> This patch reconstructs non-SIMD LOAD/STORE instruction MMIO emulation
> with analyse_intr() input. It utilizes the BYTEREV/UPDATE/SIGNEXT
> properties exported by analyse_instr() and invokes
> kvmppc_h
On Wed, Apr 25, 2018 at 07:54:39PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> Some VSX instruction like lxvwsx will splat word into VSR. This patch
> adds VSX copy type KVMPPC_VSX_COPY_WORD_LOAD_DUMP to support this.
>
> Signed-off-by: Simon Guo
Reviewed-by: Paul Mackerras
On Wed, Apr 25, 2018 at 07:54:37PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> stwsiwx will place contents of word element 1 of VSR into word
> storage of EA. So the element size of stwsiwx should be 4.
>
> This patch correct the size from 8 to 4.
>
> Signed-off-by: Simon Guo
>
On Wed, Apr 25, 2018 at 07:54:41PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> Currently HV will save math regs(FP/VEC/VSX) when trap into host. But
> PR KVM will only save math regs when qemu task switch out of CPU.
>
> To emulate FP/VEC/VSX load, PR KVM need to flush math regs
On Wed, Apr 25, 2018 at 07:54:33PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> We already have analyse_instr() which analyzes instructions for the
> instruction
> type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is
> somehow
> duplicated and it will be good
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