The previous 3 commits added support code for the Nemo motherbard
as used in the Amigaone X1000, now wire them up so the board can
be detected and initalised at boot time.
Signed-off-by: Darren Stevens
---
diff --git a/arch/powerpc/platforms/pasemi/setup.c
b/arch/powerpc/pla
Add a IRQ init routine for the Nemo board which also inits and attatches
the i8259 found in the SB600.
Signed-off-by: Darren Stevens
---
diff --git a/arch/powerpc/platforms/pasemi/setup.c
b/arch/powerpc/platforms/pasemi/setup.c
index c4a3e93..c583c17 100644
--- a/arch/powerpc/pl
The A-Eon Amigaone X1000's Nemo motherboard has an AMD SB600
connected to one of the PCI-e root ports on its PaSemi
Pwrficient 1628M SoC. Normally the SB600 southbridge would be
connected to a hidden PCI-e port on the system's northbridge,
and as a result doesn't fully comply wi
Add routines for Nemo specific devices to init at boot time, these
being board level power-off and SB600's rtc.
Also add a run time variable to prevent these being activated
if we boot on a reference board.
Signed-off-by: Darren Stevens
---diff --git a/arch/powerpc/p
The pasemi smbus controller uses PCI_FUNC(dev->devfn) to define which
number bus to attach to, however this fails when something else is
probed first, for example an ATI Radeon graphics card will claim 9 or
10 busses, including the ones the pasemi wants.
Patch the driver to call i2c_add_adapter ra
On 12/12/17 15:05, Geoff Levand wrote:
Hi Nathan,
On 12/08/2017 01:25 PM, Nathan Whitehorn wrote:
I submitted patches to libfdt that resolve this particular ABI breakage
yesterday. If the patch gets merged, newer kernels should become bootable again.
Here's the link:
https://github.com/
Currently it's possible that a thread on PPC64 LE has its endianness
flipped inadvertently to Big-Endian resulting in a crash once the process
is back from the signal handler.
If giveup_all() is called when regs->msr has the bits MSR.FP and MSR.VEC
disabled (and hence MSR.VSX disabled too) it retu
Add a selftest to check if endianness is flipped inadvertently to BE
(MSR.LE set to zero) on BE and LE machines when a trap is caught in
transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP
and MSR.VEC are zeroed (disabled).
Signed-off-by: Gustavo Romero
---
tools/testing/selft
A recent refactoring of the powerpc page fault handler caused
access to protected memory regions to indicate SEGV_MAPERR instead
of the traditional SEGV_ACCERR in the si_code field of a user-space
signal handler. This can confuse debug libraries that temporarily
change the protection of memory reg
Sounds like progress! Nice one!
I encountered several issues with this box but still believe Cell can do more.
We're at an incredible architecture right here, what concerns me most is that
we still today miss the availability of the mightyness of this machine.
Gallium 0.2 is still working for e
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