I last posted this series here,
http://marc.info/?l=linuxppc-embedded&m=150068630827162&w=2
Since then it's become apparent that NUMA allocation support was not
quite right and will require some fiddly rejigging of the early dt
parsing to make it work. So I've dropped those NUMA patches from the
On Fri, 11 Aug 2017, Josh Poimboeuf wrote:
> > + read_lock(&tasklist_lock);
> > + for_each_process_thread(g, task) {
> > + if (!klp_patch_pending(task))
> > + continue;
> > +
> > + /*
> > +* There is a small race here. We could see TIF_PATCH_PE
Hi,
On 11/08/2017 at 11:14:55 +0200, Lukáš Doktor wrote:
> The rtc-generic and opal-rtc are failing to run this test as they do not
> support all the features. Let's treat the error returns and skip to the
> following test.
>
> Theoretically the test_DATE should be also adjusted, but as it's enab
KVM currently validates the size of the VPA registered by the client
against sizeof(struct lppaca), however we align (and therefore size)
that struct to 1kB to avoid crossing a 4kB boundary in the client.
PAPR calls for sizes >= 640 bytes to be accepted. Hard code this with
a comment.
Signed-off-
Remove incorrect comment about real mode address restrictions on
powernv (bare metal), and unnecessary clamping to ppc64_rma_size.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/opal.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/plat
This removes the RMA limit on powernv platform, which constrains
early allocations such as PACAs and stacks. There are still other
restrictions that must be followed, such as bolted SLB limits, but
real mode addressing has no constraints.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/mm/hash_u
Radix MMU does not take SLB or TLB interrupts when accessing kernel
linear address. Remove this restriction for radix mode.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/setup_64.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup_
Book3S radix-mode has no SLB interrupt limitation, and hash-mode has
a 1T limitation on modern CPUs, so PACA allocation limits can be lifted.
Update the paca alloation limits. Share TLB/SLB calculation with the
stack allocation code.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/paca.c
These are unused in radix mode.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/paca.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 64401f551765..354a955ca377 100644
--- a/arch/powerpc/kern
The "lppaca" is a structure registered with the hypervisor. This
is unnecessary when running on non-virtualised platforms. One field
from the lppaca (pmcregs_in_use) is also used by the host, so move
the host part out into the paca (lppaca field is still updated in
guest mode).
Signed-off-by: Nich
Change the paca array into an array of pointers to pacas. Allocate
pacas individually.
This allows flexibility in where the PACAs are allocated. Future work
will allocate them node-local. Platforms that don't have address limits
on PACAs would be able to defer PACA allocations until later in boot
Similary to the previous patch, allocate LPPACAs individually.
We no longer allocate lppacas in an array, so this patch removes the 1kB
static alignment for the structure, and enforce the PAPR alignment
requirements at allocation time. We can not reduce the 1kB allocation size
however, due to exis
These uart_ops structures are only stored in the ops field of a
uart_port structure and this fields is const, so the uart_ops
structures can also be const.
Done with the help of Coccinelle.
---
drivers/tty/serial/21285.c |2 +-
drivers/tty/serial/apbuart.c|
These uart_ops structures are only stored in the ops field of a
uart_port structure and this fields is const, so the uart_ops
structures can also be const.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/tty/serial/ucc_uart.c |2 +-
1 file changed, 1 insertion(+),
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