Hi Hari,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.13-rc3 next-20170804]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Hari-Bathini/powerpc-prom-avoid-endian-conversi
Hi! Find below my second regression report for Linux 4.13. It lists 10
regressions I'm currently aware of (albeit in one case it's not entirely
clear yet if it's a regression in 4.13). One regression got fixed since
last weeks report. You can also find the report at
http://bit.ly/lnxregrep413 where
Hi Lukas,
Let me reply "back-to-front":
> Please cc dri-devel when proposing changes to vgaarb.c (see
> MAINTAINERS).
Sorry, will do in future.
> I'm missing some context as to the negative consequences you're
> experiencing on other arches (the cover letter merely refers to
> "quirks in ppc an
On Sat, Aug 5, 2017 at 3:06 AM, Tyrel Datwyler
wrote:
> On 08/03/2017 06:12 PM, Matt Brown wrote:
>> This adds the powernv_get_random_darn function which utilises the darn
>> instruction, introduced in POWER9. The powernv_get_random_darn function
>> is used as the ppc_md.get_random_seed on P9.
>>
Hi Christophe,
I'm not across any of the details of this so hopefully most of these
comments aren't too stupid :)
Christophe Lombard writes:
> The POWER9 core supports a new feature: ASB_Notify which requires the
> support of the Special Purpose Register: TIDR.
TIDR is defined in ISA 3.0B, wh
QEIC is supported more than just powerpc boards, so remove PPCisms.
changelog:
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
- remove include/soc/fsl/qe/qe_ic.h
Changes for v9:
- rebase
- fix the compile issue whe
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
MAINTAINERS| 6 ++
drivers/irqchip/Makefile | 1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
drivers/irqchip/irq-qeic.c | 90 --
incl
QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang
---
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c| 1 -
arch/powerpc/platforms/83xx/mpc832x_mds.c
On Mon, Jul 24, 2017 at 02:07:52PM -0500, Brijesh Singh wrote:
> From: Tom Lendacky
>
> DMA access to memory mapped as encrypted while SEV is active can not be
> encrypted during device write or decrypted during device read.
Yeah, definitely rewrite that sentence.
> In order
> for DMA to proper
On 2017/8/4 23:29, Boris Brezillon wrote:
We are planning to share more code between different NAND based
devices (SPI NAND, OneNAND and raw NANDs), but before doing that
we need to move the existing include/linux/mtd/nand.h file into
include/linux/mtd/rawnand.h so we can later create a nand.h
Hi Michael,
On Tue, Aug 01, 2017 at 08:56:18PM +1000, Michael Ellerman wrote:
> "Gautham R. Shenoy" writes:
> >
> > Subject: [v3 PATCH 1/2] powernv/powerpc:Save/Restore additional SPRs for
> > stop4 cpuidle
>
> I know it's not a big deal, but can we agree on the subject format?
>
> powerpc/
Matt Brown writes:
> On Sat, Aug 5, 2017 at 3:06 AM, Tyrel Datwyler
> wrote:
>> On 08/03/2017 06:12 PM, Matt Brown wrote:
>>> @@ -135,8 +152,9 @@ static __init int rng_create(struct device_node *dn)
>>>
>>> static __init int rng_init(void)
>>> {
>>> + unsigned long darn_test;
>>> str
From: "Gautham R. Shenoy"
Hi,
This is the fourth iteration of the patchset to enable exploitation of
stop4 idle state on POWER9 via cpuidle.
The earlier version can be found here :
[v3]: https://lkml.org/lkml/2017/7/21/209
[v2]: https://lkml.org/lkml/2017/7/19/152
[v1]: https://lkml.org/lkml/20
From: "Gautham R. Shenoy"
Currently we use the stop-api provided by the firmware to program the
SLW engine to restore the values of hypervisor resources that get lost
on deeper idle states (such as winkle). Since the deep states were
only used for CPU-Hotplug on POWER8 systems, we would program t
From: "Gautham R. Shenoy"
The stop4 idle state on POWER9 is a deep idle state which loses
hypervisor resources, but whose latency is low enough that it can be
exposed via cpuidle.
Until now, the deep idle states which lose hypervisor resources (eg:
winkle) were only exposed via CPU-Hotplug. Hen
On Fri, 2017-08-04 at 11:55 +0200, Frederic Barrat wrote:
> P9 has support for PCI peer-to-peer, enabling a device to write in the
> mmio space of another device directly, without interrupting the CPU.
>
> This patch adds support for it on powernv, by adding a new API to be
> called by drivers. Th
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